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F25D08QA Datasheet(PDF) 6 Page - Elite Semiconductor Memory Technology Inc. |
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F25D08QA Datasheet(HTML) 6 Page - Elite Semiconductor Memory Technology Inc. |
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6 / 69 page  ESMT F25D08QA Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2013 Revision: 1.1 6/69 STATUS REGISTER The Software Status Register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the Status Register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the Software Status Register. Table 2: Software Status Register Bit Name Function Default at Power-up Read/Write Status Register 0 BUSY 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 0 R 1 WEL 1 = Device is memory Write enabled 0 = Device is not memory Write enabled 0 R 2 BP0 Indicate current level of block write protection (See Table 3) 0 R/W 3 BP1 Indicate current level of block write protection (See Table 3) 0 R/W 4 BP2 Indicate current level of block write protection (See Table 3) 0 R/W 5 BP3 Indicate current level of block write protection (See Table 3) 0 R/W 6 QE 1 = Quad enabled 0 = Quad disabled 0 R/W 7 BPL 1 = BP3, BP2,BP1,BP0 are read-only bits 0 = BP3, BP2,BP1,BP0 are read/writable 0 R/W Note: 1. BUSY and WEL are read only. 2. BP0~3, QE and BPL bits are non-volatile. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If this bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions: • Power-up • Write Disable (WRDI) instruction completion • Page Program instruction completion • Sector Erase instruction completion • Block Erase instruction completion • Chip Erase instruction completion • Write Status Register instruction completion • Signal Block Lock (SBLK) instruction completion • Signal Block Unlock (SBULK) instruction completion • Gang Block Lock (GBLK) instruction completion • Gang Block Unlock (GBULK) instruction completion • Write Security Register (WRSCUR) instruction completion • Write Protect Selection (WPSEL) instruction completion BUSY The BUSY bit determines whether there is an internal Erase or Program operation in progress. A “1” for the BUSY bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Quad Enable (QE) When the Quad Enable bit is reset to “0” (factory default), WP and HOLD pins are enabled. When QE pin is set to “1”, Quad SIO2 and SIO3 are enabled. (The QE should never be set to “1” during standard and Dual SPI operation if the WP and HOLD pins are tied directly to the VDD or VSS.). When in QPI mode, QE bit is not required for setting. |
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