Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MAX1200 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part No. MAX1200
Description  5v sINGLE-sUPPLY, 1mSPS, 16-bIT sELF-cALIBRATING adc
Download  16 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
Logo 

MAX1200 Datasheet(HTML) 4 Page - Maxim Integrated Products

 
Zoom Inzoom in Zoom Outzoom out
 4 / 16 page
background image
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
4
_______________________________________________________________________________________
DIGITAL INPUT AND OUTPUT CHARACTERISTICS
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation.
Note 2: For unipolar mode, the analog input voltage, VINP, must be within 0 and VREF, VINN = VCM / 2; where VREF = VRFPS - VRFNS.
For differential mode, the analog input voltages VINP and VINN must be within 0 and VREF; where VREF = VRFPS - VRFNS. The
common-mode voltage of the inputs INP and INN is VCM = (VRFPS + VRFNS) / 2.
Note 3: RI varies inversely with sample rate.
Note 4: Minimum and maximum parameters are not tested. Guaranteed by design.
Note 5: Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%. Guaranteed by design.
Note 6: All AC specifications are shown for the differential mode.
ISOURCE = 200µA
VIN = 0 or DVDD
CONDITIONS
4
Input Capacitance
DVDD - 0.8
VIH
0.8
VIL
Input LOW Voltage
Input HIGH Voltage
DVDD
DVDD
- 0.4
- 0.03
VOH
Output High Voltage
0.8
VCLK
CLK Input LOW Voltage
AVDD - 0.8
VCLK
CLK Input HIGH Voltage
9
CCLK
CLK Input Capacitance
±0.1
±10
IIN
Digital Input Current
MIN
TYP
MAX
SYMBOL
PARAMETER
ISINK = 1.6mA
70
400
VOL
Output Low Voltage
±0.1
±10
ILEAKAGE
Three-State Leakage Current
3.5
COUT
Three-State Output Capacitance
mV
µA
pF
pF
V
V
V
V
V
pF
µA
UNITS
VIN = 0 or VDD
±1
±10
ICLK
CLK Input Current
µA
CL = 20pF
CONDITIONS
ns
187
244
301
tCH
Clock HIGH Time
ns
488
tCLK
ns
4 / fSAMPLE
tCONV
Conversion Time
Clock Period
ns
16
75
tREL
Bus Relinquish Time
ns
16
75
tAC
Data Access Time
ns
187
244
301
tCL
Clock LOW Time
ns
70
150
tOD
Output Delay
ns
1 / fCLK
tDAV
DAV Pulse Width
ns
65
145
tS
CLK-to-DAV Rising Edge
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ST_CAL = DVDD
fCLK
Cycles
17,400
tCAL
Calibration Time
ns
tCLK / 2
tACQ
Acquisition Time
TIMING CHARACTERISTICS (Figures 7, 8, 9)
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, fCLK = 2.048MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn