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MAX1198 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part No. MAX1198
Description  Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX1198 Datasheet(HTML) 5 Page - Maxim Integrated Products

 
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Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLK
0.2
×
VDD
Input Low Threshold
VIL
PD,
OE, SLEEP, T/B
0.2
×
OVDD
V
Input Hysteresis
VHYST
0.15
V
IIH
VIH = VDD = OVDD
±20
Input Leakage
IIL
VIL = 0
±20
µA
Input Capacitance
CIN
5pF
DIGITAL OUTPUTS ( D7A–D0A, D7B–D0B)
Output Voltage Low
VOL
ISINK = -200µA
0.2
V
Output Voltage High
VOH
ISOURCE = 200µA
OVDD -
0.2
V
Three-State Leakage Current
ILEAK
OE = OVDD
±10
µA
Three-State Output Capacitance
COUT
OE = OVDD
5pF
POWER REQUIREMENTS
Analog Supply Voltage Range
VDD
2.7
3.3
3.6
V
Output Supply Voltage Range
OVDD
CL = 15pF
1.7
2.5
3.6
V
Operating, fINA & B = 20MHz at -1dB FS
applied to both channels
80
95
Sleep mode
3.2
mA
Analog Supply Current
IVDD
Shutdown, clock idle, PD =
OE = OVDD
0.15
20
µA
Operating, fINA & B = 20MHz at -1dB FS
applied to both channels (Note 6)
11.5
mA
Sleep mode
2
Output Supply Current
IOVDD
Shutdown, clock idle, PD =
OE = OVDD
210
µA
Operating, fINA & B = 20MHz at -1dB FS
applied to both channels
264
314
Sleep mode
10.6
mW
Analog Power Dissipation
PDISS
Shutdown, clock idle, PD =
OE = OVDD
0.5
66
µW
Offset, VDD
±5%
±3
Power-Supply Rejection
PSRR
Gain, VDD
±5%
±3
mV/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
tDO
CL = 20pF (Notes 1, 7)
6
8.25
ns
OE Fall to Output Enable Time
tENABLE
5ns
OE Rise to Output Disable Time
tDISABLE
5ns
CLK Pulse Width High
tCH
Clock period: 10ns (Note 7)
5 ±0.5
ns
CLK Pulse Width Low
tCL
Clock period: 10ns (Note 7)
5 ±0.5
ns
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10k
Ω resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless
otherwise noted.
≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
TA = +25°C.)


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