MAX1196 datasheet(5/23 Pages) MAXIM | Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

Part No.	MAX1196

Description	Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

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Manufacturer	MAXIM [Maxim Integrated Products]

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Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________

5

ELECTRICAL CHARACTERISTICS (continued)

(VDD = OVDD = 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k

Ω

resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to TMAX,

unless otherwise noted.

≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values

are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Hysteresis

VHYST

0.15

V

IIH

VIH = VDD = OVDD

±20

Input Leakage

IIL

VIL = 0

±20

µA

Input Capacitance

CIN

5pF

DIGITAL OUTPUTS (D0A/B–D7A/B, A/B)

Output Voltage Low

VOL

ISINK = -200µA

0.2

V

Output Voltage High

VOH

ISOURCE = 200µA

OVDD -

0.2

V

Three-State Leakage Current

ILEAK

OE = OVDD

±10

µA

Three-State Output Capacitance

COUT

OE = OVDD

5pF

POWER REQUIREMENTS

Analog Supply Voltage Range

VDD

2.7

3

3.6

V

Output Supply Voltage Range

OVDD

1.7

3

3.6

V

Operating, fINA&B = 20MHz at -1dB FS

applied to both channels

29

36

Sleep mode

3

mA

Analog Supply Current

IVDD

Shutdown, clock idle, PD = OE = OVDD

0.1

20

µA

Operating, fINA&B = 20MHz at -1dB FS

applied to both channels (Note 6)

8mA

Sleep mode

3

Output Supply Current

IOVDD

Shutdown, clock idle, PD = OE = OVDD

310

µA

Operating, fINA&B = 20MHz at -1dB FS

applied to both channels

87

108

Sleep mode

9

mW

Analog Power Dissipation

PDISS

Shutdown, clock idle, PD = OE = OVDD

0.3

60

µW

Offset, VDD

±5%

±3

Power-Supply Rejection

PSRR

Gain, VDD

±5%

±3

mV/V

TIMING CHARACTERISTICS

CLK Rise to CHA Output Data

Valid

tDOA

CL = 20pF (Notes 1, 7)

6

8.25

ns

CLK Fall to CHB Output Data

Valid

tDOB

CL = 20pF (Notes 1, 7)

6

8.25

ns

Clock Rise/Fall to A/B Rise/Fall

Time

tDA/B

6ns

OE Fall to Output Enable Time

tENABLE

5ns

OE Rise to Output Disable Time

tDISABLE

5ns

CLK Pulse Width High

tCH

Clock period: 25ns (Note 7)

12.5

±1.5

ns

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