Offsets resulting from synchronous noise (such as the

conversion clock) are canceled by the MAX1134/

MAX1135s’ calibration scheme. However, because the

magnitude of the offset produced by a synchronous

signal depends on the signal’s shape, recalibration

may be appropriate if the shape or relative timing of the

clock or other digital signals change, which can occur

if more than one clock signal or frequency is used.

Distortion

Avoid degrading dynamic performance by choosing an

amplifier with distortion much less than the

MAX1134/MAX1135s’ THD (-90dB) at frequencies of

interest. If the chosen amplifier has insufficient common-

mode rejection, which results in degraded THD perfor-

mance, use the inverting configuration to eliminate errors

from common-mode voltage. Low-temperature-coeffi-

cient resistors reduce linearity errors caused by resis-

tance changes due to self-heating. To reduce linearity

errors due to finite amplifier gain, use an amplifier circuit

with sufficient loop gain at the frequencies of interest.

DC Accuracy

If DC accuracy is important, choose a buffer with an

offset much less than the MAX1134/MAX1135s’ maxi-

mum offset (±6mV), or whose offset can be trimmed

while maintaining good stability over the required tem-

perature range.

Operating Modes and Serial Interfaces

The MAX1134/MAX1135 are fully compatible with

MICROWIRE and SPI/QSPI devices. MICROWIRE and

SPI/QSPI both transmit a byte and receive a byte at the

same time. The simplest software interface requires

only three 8-bit transfers to perform a conversion (one

8-bit transfer to configure the ADC, and two more 8-bit

transfers to clock out the 16-bit conversion result).

Short Acquisition Mode (24 SCLK)

Configure short acquisition by setting M1 = 0 and M0 =

0. In short acquisition mode, the acquisition time is 5

clock cycles. The total period is 24 clock cycles per

conversion.

Long Acquisition Mode (32 SCLK)

Configure long acquisition by setting M1 = 1 and M0 =

1. In long acquisition mode, the acquisition time is 13

clock cycles. The total period is 32 clock cycles per

conversion.

Calibration Mode

A calibration is initiated through the serial interface by set-

ting M1 = 0 and M0 = 1. Calibration can be done in either

internal or external clock mode, though it is desirable that

the part be calibrated in the same mode in which it will be

used to do conversions. The part remains in calibration

mode for approximately 80,000 clock cycles unless the

calibration is aborted. Calibration is halted if RST or

SHDN goes low, or if a valid start condition occurs.

Software Shutdown

A software power-down is initiated by setting M1 = 1

and M0 = 0. After the conversion completes, the part

shuts down. It reawakens upon receiving a new start

bit. Conversions initiated with M1 = 1 and M0 = 0 (shut-

down) use the acquisition mode selected for the previ-

ous conversion.

Shutdown Mode

The MAX1134/MAX1135 may be shut down by pulling

SHDN low or by asserting software shutdown. In addi-

tion to lowering power dissipation to 4.0µW, consider-

able power can be saved by shutting down the

converter for short periods between conversions. There

is no need to perform a calibration after the converter

has been shut down unless the time in shutdown is

long enough that the supply voltage or ambient temper-

ature has changed.

Supplies, Layout, Grounding,

and Bypassing

For best system performance, use separate analog and

digital ground planes. The two ground planes should

be tied together at the MAX1134/MAX1135. Use pin 3

and pin 14 as the primary AGND and DGND, respec-

tively. If the analog and digital supplies come from the

same source, isolate the digital supply from the analog

with a low-value resistor (10

Ω).

The MAX1134/MAX1135 are not sensitive to the order

present in the absence of the other. Do not apply an

Be sure that digital return currents do not pass through

the analog ground. All return-current paths must be low

impedance. A 5mA current flowing through a PC board

ground trace impedance of only 0.05

Ω creates an error

voltage of about 250µV, or about 2LSBs error with a

±4V

full-scale system. The board layout should ensure that

digital and analog signal lines are kept separate. Do not

run analog and digital lines parallel to one another. If you

must cross one with the other, do so at right angles.

The ADC is sensitive to high-frequency noise on the

ground plane with 0.1µF. If the main supply is not ade-

quately bypassed, add an additional 1µF or 10µF low-

ESR capacitor in parallel with the primary bypass

capacitor.

16-Bit ADCs, 150ksps, 3.3V Single Supply

14

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