150ksps, 10-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs in SOT23

4

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TIMING CHARACTERISTICS (Figures 1 and 2)

PARAMETERS

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCLK Pulse Width High

38

ns

SCLK Pulse Width Low

38

ns

SCLK Fall to DOUT Transition

60

ns

SCLK Rise to DOUT Disable

100

500

ns

CNVST Rise to DOUT Enable

80

ns

CNVST Fall to MSB Valid

3.7

µs

CNVST Pulse Width

30

ns

Note 1: Unipolar input.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have

been removed.

Note 3: Offset nulled.

• • •

• • •

• • •

CNVST

SCLK

DOUT

HIGH-Z

HIGH-Z

DOUT

6k

Ω

6k

Ω

GND

DOUT

GND

Figure 1. Detailed Serial-Interface Timing Sequence

Figure 2. Load Circuits for Enable/Disable Times