asserted, the auxiliary port contained “even” samples

while the primary port contained “odd” samples. After

the RSTOUT is deasserted (which marks the start of the

DREADY clock’s reset phase), note that the order of the

samples in the ports has been reversed. The auxiliary

port also contains an out-of-sequence sample. This is a

consequence of the “swallowed” clock cycle that was

needed to resynchronize DREADY to the reset phase.

Also note that the older sample data is always in the

auxiliary port, regardless of the DREADY phase.

These examples illustrate the combinations that result

with a reset input signal of two clock cycles. It is also

possible to reset the internal MAX108 demux success-

fully with a reset pulse of only one clock cycle, provid-

ed that the setup time and hold-time requirements are

met with respect to the sample clock. However, this is

not recommended when additional external demuxes

are used.

Note that many external demuxes require their reset

signals to be asserted while they are clocked, and may

require more than one clock cycle of reset. More impor-

tantly, if the phase of the DREADY clock is such that a

clock pulse will be “swallowed” to resynchronize, then

no reset output will occur at all. In effect, the RSTOUT

signal will be “swallowed” with the clock pulse. The

best method to ensure complete system reset is to

assert RSTIN for the appropriate number of DREADY

clock cycles required to complete reset of the external

demuxes.

Die Temperature Measurement

For applications that require monitoring of the die tem-

perature, it is possible to determine the die temperature

of the MAX108 under normal operating conditions by

(nominal) currents that are designed to be equal at

+27°C. These currents are derived from the MAX108’s

directly proportional to the absolute temperature. These

currents are derived from PNP current sources refer-

nected to GNDI. The contacts ICONST and IPTAT may

be left open because internal catch diodes prevent sat-

uration of the current sources. The simplest method of

determining the die temperature is to measure each

±5V, 1.5Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

______________________________________________________________________________________

23

Figure 19. Reset Output Timing in Demuxed DIV2 Mode (DREADY Realigned)

NOTE: DREADY PHASE WAS ADJUSTED TO MATCH THE RESET PHASE BY “SWALLOWING” ONE INPUT CLOCK CYCLE.

THE AUXILIARY PORT CONTAINS AN OUT-OF-SEQUENCE SAMPLE AS A RESULT OF THE DELAY.

CLK-

CLK+

n

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

n+10

n+11

n+12

n+13

ADC SAMPLE NUMBER

ADC SAMPLES ON THE RISING EDGE OF CLK+

CLOCK PULSE “SWALLOWED”

OUT-OF-SEQUENCE SAMPLE

CLK

DREADY

DREADY+

DREADY-

RSTIN+

RSTIN-

RSTOUT+

RSTOUT-

RESET

INPUT

n-1

n+1

n-2

AUXILIARY

DATA PORT

PRIMARY

DATA PORT

n

n+2

n+4

RESET OUT

DATA PORT