_______________Detailed Description

Converter Operation

The parallel or “flash” architecture used by the MAX101A

provides the fastest multibit conversion of all common

integrated ADC designs. The basic element of a flash, as

with all other ADC architectures, is the comparator, which

has a positive input, a negative input, and an output. If

the voltage at the positive input is higher than the nega-

tive input (connected to a reference), the output will be

high. If the positive input voltage is lower than the refer-

ence, the output will be low. A typical n-bit flash consists

at 1LSB increments from the bottom to the top of the ref-

erence ladder. For n = 8, there are 255 comparators.

For any input voltage, all the comparators with negative

inputs connected to the reference ladder below the

input voltage will have outputs of 1 and all comparators

with negative inputs above the input voltage will have

outputs of 0. Decode logic is provided to convert this

information into a parallel n-bit digital word (the output)

corresponding to the number of LSBs (minus 1) that the

input voltage is above the bottom of the ladder.

The comparators contain latch circuitry and are

clocked. This allows the comparators to function as

described previously when, for example, clock is low.

When clock goes high (samples) the comparator will

latch and hold its state until the clock goes low again.

The MAX101A uses a monolithic, dual-interleaved par-

allel quantizer chip with two separate 8-bit converters.

These converters deliver results to the A and B output

latches on alternate negative edges of the input clock.

Track/Hold

As with all ADCs, if the input waveform is changing

rapidly during the conversion, the effective bits and

SNR will decrease. The MAX101A has an internal

track/hold (T/H) that increases attainable effective-bits

performance and allows more accurate capture of ana-

log data at high conversion rates.

The internal T/H circuit provides two important circuit

functions for the MAX101A:

1) Its nominal voltage gain of 4 reduces the input dri-

ving signal to ±250mV differential (assuming a

±0.95V reference).

2) It provides a differential 50

Ω input that allows easy

interface to the MAX101A.

Data Flow

The MAX101A’s internal T/H amplifier samples the ana-

log input voltage for the ADC to convert. The T/H is split

into two sections that operate on alternate negative

clock edges. The input clock, CLK, is conditioned by

the T/H and fed to the A/D section. The output clock,

DCLK, used for output data timing, will be divided by 2

or 10 from the input clock (Table 1). This results in an

output data rate of 250Mbps on each output port in nor-

mal mode and 50Mbps in test mode. The differential

inputs, AIN+ and AIN-, are tracked continuously

between data samples. When a negative strobe edge is

sensed, one-half of the T/H goes into hold mode (Figure

4). When the strobe is low, the just-acquired sample is

presented to the ADC’s input comparators. Internal pro-

cessing of the sampled data takes an additional 15

clock cycles before it is available at the outputs, AData

and BData. See Figures 1–3 for timing.

__________Applications Information

Analog Input Ranges

Although the normal operating range is ±250mV, the

MAX101A can be operated with up to ±500mV on each

input with respect to ground. This extended input level

includes the analog signal and any DC common-mode

voltage.

To obtain full-scale digital output with differential

input drive, a nominal +250mV must be applied

between AIN+ and AIN-. That is, AIN+ = +125mV and

AIN- = -125mV (with no DC offset). Mid-scale digital

output code occurs when there is no voltage difference

across the analog inputs. Zero-scale digital output

code, with differential -250mV drive, occurs when AIN+

= -125mV and AIN- = +125mV. Table 2 shows how the

output of the converter stays at all ones (full scale)

when over-ranged or all zeros (zero scale) when under-

ranged.

Table 1. Output Mode Control

* Input clocks (CLK, CLK) = 500MHz for all above combinations. In

all modes, the output clock DCLK will be a 50% duty-cycle signal.

500Msps, 8-Bit ADC with Track/Hold

______________________________________________________________________________________

11

DIV10

DCLK*

(MHz)

DESCRIPTION

OPEN

250

AData and BData valid on oppo-

site DCLK edges (AData on rise,

BData on fall).

GND

50

AData and BData valid on oppo-

site DCLK edges (AData on rise,

BData on fall). Data sampled at

input CLK rate but 4 out of every

5 samples discarded.

MODE

Normal

Divide

by 2

Test

Divide

by 10