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NCP4688DSN25T1G Datasheet(PDF) 2 Page - ON Semiconductor |
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NCP4688DSN25T1G Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 14 page NCP4688 http://onsemi.com 2 Figure 2. Simplified Schematic Block Diagram Current Limit Vin GND Vref CE Vout Noise Reduction NCP4688xxxx Current Limit Vin GND Vref CE Vout Noise Reduction NCP4688D Table 1. PIN FUNCTION DESCRIPTION Pin No. SOT−23−5 Pin No. DFN 1x1 Pin Name Description 1 4 VIN Input pin 2 2 GND Ground pin 3 3 CE Chip enable pin (“H” active) 4 NC Non connected 5 1 VOUT Output pin *EP EP Exposed Pad (leave floating or connect to GND) Table 2. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage VIN 0 − 6 V V Output Voltage VOUT −0.3 to VIN + 0.3 V Chip Enable Input VCE 0 − 6 V V Power Dissipation SOT−23−5 PD 420 mW Power Dissipation mDFN 1.0 x 1.0 mm 400 Junction Temperature TJ −40 to 150 °C Storage Temperature TSTG −55 to 125 °C ESD Capability, Human Body Model (Note 1) ESDHBM 2000 V ESD Capability, Machine Model (Note 1) ESDMM 200 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78 |
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