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DG444CJ Datasheet(PDF) 6 Page - Maxim Integrated Products |
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DG444CJ Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 8 page ______________________________________________Timing Diagrams/Test Circuits tOFF 0.8 x VOUT VOUT 0.8 x VOUT tf < 20ns tr < 20ns 50% 0V 0V +3V SWITCH OUTPUT LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. tON SWITCH INPUT LOGIC INPUT +3V IN +5V V- -15V ( ) RL CL VOUT S CL INCLUDES FIXTURE AND STRAY CAPACITANCE. GND REPEAT TEST FOR CHANNELS 2, 3, AND 4. VOUT = VD RL RL + rDS(ON) LOGIC INPUT VL +15V V+ D DG444 DG445 Figure 2. Switching Time __________Applications Information General Operation 1. Switches are open when power is off. 2. IN, D, and S should not exceed V+ or V-, even with the power off. 3. Switch leakage is from each analog switch terminal to V+ or V-, not to other switch terminals. Operation with Supply Voltages Other Than ±15V Using supply voltages other than ±15V will reduce the analog signal range. The DG444/DG445 switches oper- ate with ±4.5V to ±20V bipolar supplies or with a +10V to +30V single supply; connect V- to 0V when operating with a single supply. Also, all device types can operate with unbalanced supplies such as +24V and -5V. VL must be connected to +5V to be TTL compatible, or to V+ for CMOS-logic level inputs. The Typical Operating Characteristics graphs show typical on-resistance with ±20V, ±15V, ±10V, and ±5V supplies. (Switching times increase by a factor of two or more for operation at ±5V.) Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings because stresses beyond the list- ed ratings may cause permanent damage to the devices. Always sequence V+ on first, followed by VL , V-, and logic inputs. If power-supply sequenc- ing is not possible, add two small, external signal diodes in series with supply pins for overvoltage protection (Figure 1). Adding diodes reduces the analog signal range to 1V below V+ and 1V above V-, but low switch resistance and low leakage char- acteristics are unaffected. Device operation is unchanged, and the difference between V+ and V- should not exceed +44V. Improved, Quad, SPST Analog Switches 6 _______________________________________________________________________________________ _____________________Pin Description V+ D V- S Vg Figure 1. Overvoltage Protection Using External Blocking Diodes 2, 15, 10, 7 Positive Supply-Voltage Input— connected to substrate V+ 13 Logic Supply-Voltage Input VL 12 Ground GND 5 Negative Supply-Voltage Input V- 4 PIN Source Outputs S1-S4 3, 14, 11, 6 Drain Outputs D1-D4 Logic Control Inputs IN1-IN4 1, 16, 9, 8 FUNCTION NAME |
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