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TDA1566 Datasheet(PDF) 17 Page - NXP Semiconductors |
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TDA1566 Datasheet(HTML) 17 Page - NXP Semiconductors |
17 / 46 page TDA1566_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 20 August 2007 17 of 46 NXP Semiconductors TDA1566 I2C-bus controlled dual channel/single channel amplifier 6.5 Timing waveforms 6.5.1 Start-up and shutdown To prevent switch-on or switch-off pop noise, the capacitor on the SVR pin CSVR is used for smooth start-up and shutdown. During start-up and shutdown the output voltage tracks the SVR voltage. With IB1[D7] = 0 the time constant made with the SVR capacitor can be increased to reduce turn on transients at the load. Consequently the start-up time td(mute_off) increases with approximately 420 ms (VP = 14.4 V, CSVR =22 µF, Tamb =25 °C). Note that in non-I2C-bus mode the IB1[D7] = 0 setting will be used. Increasing CSVR results in a longer start-up and shutdown time. Note that a larger SVR capacitor value will also result in a longer DC load detection cycle. Table 19. Data bytes Bit Data byte DB1 channel 1 Data byte DB2 channel 2 Data byte DB3 both channels D7 0 no AC load detected 0 no AC load detected 0 TDA1566 in mute or operating (IB1[D0] = 1) 1 AC load detected 1 AC load detected 1 power-on reset has occurred or TDA1566 in standby (IB1[D0] = 0) D6 0 no speaker fault 0 no speaker fault 0 below maximum temperature 1 speaker fault 1 speaker fault 1 maximum temperature protection activated D5 0 amplifier load (D4 = 0) 0 amplifier load (D4 = 0) 0 no temperature warning not valid (D4 = 1) not valid (D4 = 1) 1 line driver load (D4=0) 1 line driver load (D4=0) 1 temperature pre-warning active open load (D4 = 1) open load (D4 = 1) D4 0 amplifier load (D5 = 0) 0 amplifier load (D5 = 0) 0 SVR below VP /2 line driver load (D5=1) line driver load (D5=1) 1 not valid (D5 = 0) 1 not valid (D5 = 0) 1 SVR above VP /2 open load (D5 = 1) open load (D5 = 1) D3 0 no shorted load 0 no shorted load 0 invalid DC load data 1 shorted load 1 shorted load 1 valid DC load data D2 0 no output offset 0 no output offset reserved for test 1 output offset detected 1 output offset detected D1 0 no short to VP 0 no short to VP reserved for test 1 short to VP 1 short to VP D0 0 no short to ground 0 no short to ground reserved for test 1 short to ground 1 short to ground |
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