IRFHM8228PbF

7

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June 30, 2014

The typical application topology for this product is the synchronous buck converter. These converters operate at high

frequencies (typically around 400 kHz). During turn-on and turn-off switching cycles, the high di/dt currents circulating in

the parasitic elements of the circuit induce high voltage ringing which may exceed the device rating and lead to

undesirable effects. One of the major contributors to the increase in parasitics is the PCB power circuit inductance.

This section introduces a simple guideline that mitigates the effect of these parasitics on the performance of the circuit

and provides reliable operation of the devices.

To reduce high frequency switching noise and the effects of Electromagnetic Interference (EMI) when the control

MOSFET (Q1) is turned on, the layout shown in Figure 19 is recommended. The input bypass capacitors, control

MOSFET and output capacitors are placed in a tight loop to minimize parasitic inductance which in turn lowers the

amplitude of the switch node ringing, and minimizes exposure of the MOSFETs to repetitive avalanche conditions.

Fig 19. Placement and Layout Guidelines

Placement and Layout Guidelines