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P4C1299-25PMB Datasheet(PDF) 3 Page - Pyramid Semiconductor Corporation

Part # P4C1299-25PMB
Description  ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
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Manufacturer  PYRAMID [Pyramid Semiconductor Corporation]
Direct Link  http://www.pyramidsemiconductor.com
Logo PYRAMID - Pyramid Semiconductor Corporation

P4C1299-25PMB Datasheet(HTML) 3 Page - Pyramid Semiconductor Corporation

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P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
Page 3
Document #SRAM144 REV OR
DATA RETEnTIOn CHARACTERISTICS (P4C1299L Only)
DATA RETEnTIOn WAVEFORM
Sym Parameter
Test Conditions
Min
Typ* V
CC=
Max V
CC=
Unit
2.0V
3.0V
2.0V
3.0V
V
DR
V
CC for Data Retention
2.0
V
I
CCDR
Data Retention Current
CE
1,2 ≥ VCC -0.2V,
V
IN ≥ VCC -0.2V
or V
IN ≤ 0.2V
10
15
1000
2000
µA
t
CDR
Chip Deselect to Data Retention Time
0
ns
t
R
Operation Recovery Time
t
RC
§
ns
* T
A = +25°C
§ t
RC = Read Cycle Time
† This Parameter is guaranteed but not tested
POWER DISSIPATIOn CHARACTERISTICS VS. SPEED
Sym Parameter
Temperature Range
-15
-20
-25
-35
-45
Unit
I
CC
Dynamic Operating Current*
Commercial
160
125
115
110
110
mA
Industrial
160
135
120
115
115
mA
Military
160
150
120
120
120
mA
* V
CC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1,2 = VIL
Sym Parameter
-15
-20
-25
-35
-45
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
t
RC
Read Cycle Time
15
20
25
35
45
ns
t
AA
Address Access Time
15
20
25
35
45
ns
t
AC
Chip Enable Access Time
15
20
25
35
45
ns
t
OH
Output Hold from Address Change
3
3
3
3
3
ns
t
LZ
Chip Enable to Output in Low Z
3
3
3
3
3
ns
t
HZ
Chip Disable to Output in High Z
8
10
15
15
20
ns
t
OE
Output Enable Low to Data Valid
8
10
15
25
30
ns
t
OLZ
Output Enable Low to Low Z
0
0
0
0
0
ns
t
OHZ
Output Enable High to High Z
9
9
15
20
20
ns
t
PU
Chip Enable to Power Up Time
0
0
0
0
0
ns
t
PD
Chip Disable to Power Down
15
20
25
35
45
ns
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC = 5V ± 10%, All Temperature Ranges)
(2)


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