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P4C1257L20CI Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C1257L20CI Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
1 / 11 page Document # SRAM137 REV 01 Revised June 2013 P4C1257/P4C1257L ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES Full CMOS High Speed (Equal Access and Cycle Times) – 12/15/20/25 ns (Commercial) – 12/15/20/25 ns (Industrial) – 25/35/45/55/70 ns (Military) Single 5V±10% Power Supply Data Retention with 2.0V Power Supply (P4C1257L) Separate Data I/O Three-State Output Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP, SOJ – 28-Pin 350x550 mil LCC – 28-Pin Flatpack FUnCTIOnAL BLOCk DIAgRAM PIn COnFIgURATIOnS DIP (P4, C4) SOJ (J4) LCC (L5) DESCRIPTIOn The P4C1257/P4C1257L are 256Kx1-bit ultra high-speed static RAMs. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained for supply voltages down to 2.0V, typically drawing 10µA. Access times as fast as 12 nanoseconds are available, greatly enhancing system speeds. The P4C1257/P4C1257L are available in 24-pin 300 mil DIP and SOJ, 28-pin LCC and Flatpack packages, provid- ing excellent board level densities. |
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