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P4C1281 Datasheet(PDF) 5 Page - Pyramid Semiconductor Corporation |
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P4C1281 Datasheet(HTML) 5 Page - Pyramid Semiconductor Corporation |
5 / 11 page P4C1281/P4C1282 - ULTRA HIGH SPEED 64K x 4 CMOS STATIC RAMS Page 5 Document # SRAM136 REV OR TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED) (10, 11, 12) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 12. Write Cycle Time is measured from the last valid address to the first transitioning address. TIMIng WAVEFORM OF WRITE CYCLE nO. 2 (CE COnTROLLED) (10, 11, 12) |
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