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P4C164LL-9003ILF Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C164LL-9003ILF Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
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1 / 10 page  Document # SRAM116 REV 04 Revised June 2014 P4C164LL VERY LOW POWER 8Kx8 STATIC CMOS RAM FEATURES V CC Current (Commercial/Industrial) — Operating: 55 mA — CMOS Standby: 3 µA Access Times —80/100 (Commercial or Industrial) —90/120 (Military) Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CE 1, CE2 and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —28-Pin 300 and 600 mil DIP —28-Pin 330 mil SOP FUnCTIOnAL BLOCk DIAgRAM PIn COnFIgURATIOnS DIP (P5, P6, C5-1), SOP (S5) TOP VIEW DESCRIPTIOn The P4C164LL is a 64K density low power CMOS static RAM organized as 8Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 80 and 100 ns are available for commercial and industrial temperatures; access times of 90 and 100 ns are available for military temperature. CMOS is utilized to reduce power consumption to a low level. The P4C164LL device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A 0 to A12. Reading is accomplished by device selection (CE 1 LOW, CE 2 HIGH ) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory loca- tion is presented on the data input/output pins. The input/ output pins stay in the HIGH Z state when either CE 1 or OE is HIGH or WE or CE 2 is LOW. Package options for the P4C164LLinclude 28-pin 300 and 600 mil DIP and 28-pin 330 mil SOP packages. |
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