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P3C1256L85SNMLF Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation |
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P3C1256L85SNMLF Datasheet(HTML) 6 Page - Pyramid Semiconductor Corporation |
6 / 11 page P3C1256L - 32K x 8 STATIC CMOS RAM Page 6 Document # SRAM143 REV A AC TEST COnDITIOnS TRUTH TABLE TIMIng WAVEFORM OF WRITE CyCLE nO. 2 (CE COnTROLLED)(10) Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Mode CE OE WE I/O Power Standby H x x High Z Standby Standby x x x High Z Standby D OUT Disabled L H H High Z Active Read L L H D OUT Active Write L x L High Z Active Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. note: Because of the high speed of the P3C1256L, care must be taken when testing this device; an inadequate setup can cause a normal function- ing part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at the comparator input, and a 589Ω resistor must be used in series with D OUT to match 639Ω (Thevenin Resistance). |
Similar Part No. - P3C1256L85SNMLF |
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Similar Description - P3C1256L85SNMLF |
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