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M5-512/192-10VI Datasheet(PDF) 9 Page - Lattice Semiconductor

Part # M5-512/192-10VI
Description  Fifth Generation MACH Architecture
Download  47 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

M5-512/192-10VI Datasheet(HTML) 9 Page - Lattice Semiconductor

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MACH 5 Family
9
MACH 5 TIMING MODEL
The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5
device, and at the same time, be easy to understand. This model accurately describes all
combinatorial and registered paths through the device, making a distinction between
internal
feedback and external feedback. A signal uses internal feedback when it is fed back into the switch
matrix or block without having to go through the output buffer. The input register specifications
are also reported as internal feedback. When a signal is fed back into the switch matrix after having
gone through the output buffer, it is using external feedback.
The parameter, tBUF, is defined as the time it takes to go through the output buffer to the I/O pad.
If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is
followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived.
For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 5 timing model is
shown in Figure 7. Refer to the Technical Note entitled MACH 5 Timing and High Speed Design
for a more detailed discussion about the timing parameters.
INPUT REG/
INPUT LATCH
tSIR (S/A)
tHIR (S/A)
tSIL
tHIL
tSRR
tCES
tCEH
tCO (S/A) i
tPDILi
tGOAi
tSRi
tBLK
tSEG
CE
SR
(External Feedback)
(Internal Feedback)
Q
tS (S/A)
tH (S/A)
tSAL
tHAL
tSRR
tCES
tCEH
tPDi
tCO (S/A) i
tPDLi
tGOAi
tSRi
COMB/DFF/
LATCH
CE
SR
tPL1
tPL2
tPL3
IN
OUT
tPT
tEA
tER
tBUF
tSLW
PIN CLK
Q
20446G-014
Figure 7. MACH 5 Timing Model


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