 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LTM9011-14 Datasheet(PDF) 6 Page - Linear Technology |
|
||||||||||||||||||||||||||||||
LTM9011-14 Datasheet(HTML) 6 Page - Linear Technology |
|
|
6 / 40 page  LTM9011-14/ LTM9010-14/LTM9009-14 6 9009101114fb For more information www.linear.com/LTM9011-14 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS LTM9011-14 LTM9010-14 LTM9009-14 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 582 632 476 508 395 450 mA IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 54 98 62 108 52 96 62 106 50 94 58 104 mA mA PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode 2-Lane Mode, 3.5mA Mode l l 1145 1224 1249 1332 950 1030 1026 1105 801 880 914 997 mW mW PSLEEP Sleep Mode Power 2 2 2 mW PNAP Nap Mode Power 170 170 170 mW PDIFFCLK Power Decrease With Single-Ended Encode Mode Enabled (No Decrease for Sleep Mode) 40 40 40 mW TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS LTM9011-14 LTM9010-14 LTM9009-14 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX fS Sampling Frequency (Notes 10,11) l 5 125 5 105 5 80 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns tAP Sample-and-Hold Acquisition Delay Time 0 0 0 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output) tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 2-Lanes, 14-Bit Serialization 2-Lanes, 12-Bit Serialization 1-Lane, 16-Bit Serialization 1-Lane, 14-Bit Serialization 1-Lane, 12-Bit Serialization 1/(8 • fS) 1/(7 • fS) 1/(6 • fS) 1/(16 • fS) 1/(14 • fS) 1/(12 • fS) s s s s s s tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles |
Similar Part No. - LTM9011-14_15 |
|
Similar Description - LTM9011-14_15 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
