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RFFC5071A/2A

DS140110

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.

Theory of Operation

The RFFC5071A and RFFC5072A are wideband RF frequency converter chips which include a fractional-N synthesizer and a

low noise VCO core. The RFFC5071A has an LO signal multiplexer, two LO buffer circuits, and two RF mixers. The RFFC5072A

has a single LO buffer circuit and one RF mixer. Both devices have an integrated voltage reference and low drop out regulators

supplying critical circuit blocks such as the VCOs and synthesizer. Synthesizer programming, device configuration and control

are achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a simple 3-

wire serial interface.

VCO

The VCO core in the RFFC5071A and RFFC5072A consists of three VCOs which, in conjunction with the integrated LO dividers

of /2 to /32, cover the LO range of 85MHz to 4200MHz. Each VCO has 128 overlapping bands which are used to achieve low

VCO gain and optimal phase noise performance across the whole tuning range. The chip automatically selects the correct VCO

(VCO auto-select) and VCO band (VCO coarse tuning) to generate the desired LO frequency based on the values programmed

into the PLL1 and PLL2 registers banks.

The VCO auto-select and VCO coarse tuning are triggered every time ENBL is taken high, or if the PLL re-lock self clearing bit is

programmed high. Once the correct VCO and band have been selected the PLL will lock onto the correct frequency. During the

band selection process, fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is

oscillating approximately at the correct frequency. The output of this band selection, CT_CAL, is made available in the read-

back register. A value of 127 or 0 in this register indicates that the coarse tuning was unsuccessful, and this will also be indi-

cated by the CT_FAILED flag also available in the read-back register. A CT_CAL value between 1 and 126 indicates a success-

ful calibration, the actual value being dependent on the desired frequency as well as process variation for a particular device.

The band select process will center the VCO tuning voltage at about 0.8V, compensating for manufacturing tolerances and pro-

cess variation as well as environmental factors including temperature. The VCOs have temperature compensation circuits so

the PLL will hold lock over the entire operating temperature range of -40°C to +85°C. This is true regardless of the tempera-

ture at which the VCO band selection is performed. The VCO gain is also held stable across temperature, maintaining consis-

tent loop bandwidth and synthesizer phase noise.

The RFFC5071A and RFFC5072A feature a differential LO input to allow the mixer to be driven from an external LO source. The

fractional-N PLL can be used with an external VCO driven into this LO input, which may be useful to reduce phase noise in

some applications. This may also require an external op-amp, dependant on the tuning voltage required by the external VCO.

In the RFFC5071A the LO signal is routed to mixer 1, mixer 2, or both mixers depending on the state of the MODE pin (or MODE

bit if under software control) and the value of the FULLD bit. Setting FULLD high puts the device into Full Duplex mode and both

mixers are enabled.

Fractional-N PLL

The RFFC5071A and RFFC5072A contain a charge pump-based fractional-N phase locked loop (PLL) for controlling the three

VCOs. The PLL includes automatic calibration systems to counteract the effects of process and environmental variations,

ensuring repeatable loop response and phase noise performance. As well as the VCO auto-select and coarse tuning, there is a

loop filter calibration mechanism which can be enabled if required. This operates by adjusting the charge pump current to

maintain loop bandwidth. This can be useful for applications where the LO is tuned over a wide frequency range.

The PLL has been designed to use a reference frequency of between 10MHz and 104MHz from an external source, which is

typically a temperature controlled crystal oscillator (TCXO). A reference divider (divide by 1 to divide by 7) is supplied and

should be programmed to limit the frequency at the phase detector to a maximum of 52MHz.

Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the

label PLL2. For the RFFC5071A these banks are used to program mixer 1 and mixer 2 respectively, and are selected automati-

cally as the mixer is selected using MODE. For the RFFC5072A mixer 2 and register bank PLL2 are normally used.