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LTC3835-1 Datasheet(PDF) 10 Page - Linear Technology |
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LTC3835-1 Datasheet(HTML) 10 Page - Linear Technology |
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10 / 28 page  LTC3835-1 10 38351fc OPERATION (Refer to Functional Diagram) Light Load Current Operation (Burst Mode Operation, Pulse-Skipping, or Continuous Conduction) (PLLIN/MODE Pin) The LTC3835-1 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/ MODE pin to a DC voltage below 0.8V (e.g., SGND). To select forced continuous operation, tie the PLLIN/MODE pin to INTVCC. To select pulse-skipping mode, tie the PLLIN/MODE pin to a DC voltage greater than 0.8V and less than INTVCC – 0.5V. When the LTC3835-1 is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-tenth of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the aver- age inductor current is lower than the load current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.4V, the internal sleep signal goes high (enabling “sleep” mode) and both external MOSFETs are turned off. The ITH pin is then disconnected from the output of the EA and “parked” at 0.425V. In sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC3835-1 draws to only 80μA. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the ITH pin is reconnected to the output of the EA, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When the LTC3835-1 is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IR) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative, thus operating in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous operation has the advantages of lower output ripple and less interference to audio circuitry. In forced continuous mode, the output ripple is independent of load current. When the PLLIN/MODE pin is connected for pulse-skip- ping mode or clocked by an external clock source to use the phase-locked loop (see Frequency Selection and Phase-Locked Loop section), the LTC3835-1 operates in PWM pulse-skipping mode at light loads. In this mode, constant-frequency operation is maintained down to ap- proximately 1% of designed maximum output current. At very light loads, the current comparator ICMP may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (PLLLPF and PLLIN/MODE Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency opera- tion increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3835-1’s controllers can be selected using the PLLLPF pin. IfthePLLIN/MODEpinisnotbeingdrivenbyanexternalclock source, the PLLLPF pin can be floated, tied to INTVCC, or tied to SGND to select 400kHz, 530kHz or 250kHz, respectively. A phase-locked loop (PLL) is available on the LTC3835-1 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. In this case, a series R-C should be connected between the PLLLPF pin and SGND to serve as the PLL’s loop filter. The LTC3835-1 phase detector adjusts the voltage on the PLLLPF pin to align the turn-on of the external top MOSFET to the rising edge of the synchronizing signal. |
Similar Part No. - LTC3835-1_15 |
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Similar Description - LTC3835-1_15 |
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