Electronic Components Datasheet Search |
|
UPD784054 Datasheet(PDF) 35 Page - NEC |
|
UPD784054 Datasheet(HTML) 35 Page - NEC |
35 / 86 page µPD784054(A) 35 (2) 3-wire serial I/O mode This mode is to start transmission when the master device makes a serial clock active and to communicate 1-byte data in synchronization with this clock. The interface in this mode communicates with devices that have conventional clocked serial interface. Basically, communication is performed by using three lines: serial clock (SCK) and two serial data (SI and SO) lines. To connect two or more devices, a handshake line is necessary. Figure 7-8. Block Diagram in 3-Wire Serial I/O Mode Internal bus Direction control circuit Shift register SIO1, SIO2 Output latch Serial clock counter Interrupt generation circuit INTCSI1, INTCSI2 Serial clock control circuit 1/2m 1/2n+1 fCLK SI1, SI2 SO1, SO2 SCK1, SCK2 Remark fCLK: internal system clock n = 0 to 11 m = 1, 16 to 30 |
Similar Part No. - UPD784054 |
|
Similar Description - UPD784054 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |