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LF3330 Datasheet(PDF) 3 Page - LOGIC Devices Incorporated

Part No. LF3330
Description  Vertical Digital Image Filter
Download  15 Pages
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Maker  LODEV [LOGIC Devices Incorporated]
Homepage  http://www.logicdevices.com
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LF3330 Datasheet(HTML) 3 Page - LOGIC Devices Incorporated

 
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DEVICES INCORPORATED
Video Imaging Products
3
LF3330
Vertical Digital Image Filter
11/08/2001–LDS.3330-M
SIGNAL DEFINITIONS
Power
VCC and GND
+3.3 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
Inputs
DIN11-0 — Data Input
DIN11-0 is the 12-bit registered data
input port. Data is latched on the rising
edge of CLK.
VB11-0 — Field Filtering Data Input
VB11-0 is the 12-bit registered data
input port used only when implement-
ing Odd and Even Field Filtering (see
Functional Description section for a full
discussion). Data is latched on the
rising edge of CLK.
CF11-0 — Coefficient Input
CF11-0 is used to load data into the
coefficient banks and configuration/
control registers. Data present on
CF11-0 is latched into the LF InterfaceTM
on the rising edge of CLK when LD is
LOW (see the LF InterfaceTM section for
a full discussion).
CA7-0 — Coefficient Address
CA7-0 determines which row of data in
the coefficient banks is fed to the
multipliers. CA7-0 is latched into the
Coefficient Address Register on the
rising edge of CLK when CEN is LOW.
Outputs
DOUT15-0 — Data Output
DOUT15-0 is the 16-bit registered data
output port.
COUT11-0 — Cascade Data Output
COUT11-0 is a 12-bit cascade
output port. COUT11-0 on one
device should be connected to
DIN11-0 of another LF3330.
Controls
LD — Coefficient Load
When LD is LOW, data on CF11-0
is latched into the LF InterfaceTM
on the rising edge of CLK. When
LD is HIGH, data can not be
latched into the LF InterfaceTM.
When enabling the LF InterfaceTM
for data input, a HIGH to LOW
transition of LD is required in
order for the input circuitry to
function properly. Therefore, LD
must be set HIGH immediately
after power up to ensure proper
operation of the input circuitry
(see the LF InterfaceTM section for
a full discussion).
PAUSE — LF InterfaceTM Pause
When PAUSE is HIGH, the LF
InterfaceTM loading sequence is halted
until PAUSE is returned to a LOW
state. This effectively allows the user
to load coefficients and control
registers at a slower rate than the
master clock (see the LF InterfaceTM
section for a full discussion).
CEN — Coefficient Address Enable
When CEN is LOW, data on CA7-0 is
latched into the Coefficient Address
Register on the rising edge of CLK.
When CEN is HIGH, data on CA7-0 is
not latched and the register’s contents
will not be changed.
FIGURE 2.
INPUT FORMATS
11 10 9
2
1
0
–2
11
(Sign)
2
10
2
9
2
2
2
1
2
0
11 10 9
2
1
0
–2
0
(Sign)
2
–1 2–2
2
–9 2–10 2–11
Input Data
Coefficient Data
FIGURE 3. ACCUMULATOR FORMAT
31 30 29
2
1
0
–2
20
(Sign)
2
19 218
2
–9 2–10 2–11
Accumulator Output
TABLE 1.
OUTPUT FORMATS
SLCT4-0
S15 S14 S13
· · ·
S8
S7
· · ·
S2
S1
S0
00000
F15
F14
F13
· · ·
F8
F7
· · ·
F2
F1
F0
00001
F16
F15
F14
· · ·
F9
F8
· · ·
F3
F2
F1
00010
F17
F16
F15
· · ·
F10
F9
· · ·
F4
F3
F2
·
·
·
·
··
··
·
·
·
·
·
··
··
·
·
·
·
·
··
··
·
01110
F29
F28
F27
· · ·
F22
F21
· · ·
F16
F15
F14
01111
F30
F29
F28
· · ·
F23
F22
· · ·
F17
F16
F15
10000
F31
F30
F29
· · ·
F24
F23
· · ·
F18
F17
F16


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