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LTC2408IG Datasheet(PDF) 11 Page - Linear Technology |
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LTC2408IG Datasheet(HTML) 11 Page - Linear Technology |
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11 / 36 page  11 LTC2404/LTC2408 Converter Operation Cycle The LTC2404/LTC2408 are low power, 4-/8-channel delta- sigma analog-to-digital converters with easy-to-use 4-wire interfaces. Their operation is simple and made up of four states. The converter operation begins with the conversion, followed by a low power sleep state and concluded with the data output (see Figure 1). Channel selection may be performed while the device is in the sleep state or at the conclusion of the data output state. The interface consists of serial data output (SDO), serial clock (CLK/SCK), chip select (CSADC/CSMUX) and data input (DIN). By tying SCK to CLK and CSADC to CSMUX, the interface requires only four wires. Initially, the LTC2404 or LTC2408 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in the sleep state, power consumption is reduced by an order of magnitude. The part remains in the sleep state as long as CSADC is logic HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Channel selection for the next conversion cycle is per- formed while the device is in the sleep state or at the end of the data output state. A specific channel is selected by applying a 4-bit serial word to the DIN pin on the rising edge of CLK while CSMUX is HIGH, see Figure 3 and Table 3. The channel is selected based on the last four bits clocked into the DIN pin before CSMUX goes low. If DIN is all 0’s, the previous channel remains selected. In the example, Figure 3, the MUX channel is selected during the sleep state, just before the data output state begins. Once the channel selection is complete, the device remains in the sleep state as long as CSADC remains HIGH. Once CSADC is pulled low, the device begins outputting the conversion result. There is no latency in the conversion result. Since there is no latency, the first conversion following a change in input channel is valid and corre- sponds to that channel. The data output corresponds to the conversion just performed. This result is shifted out on the serial data output pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK, see Figure 3. The data output state is concluded once 32 bits are read out of the ADC or when CSADC is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CSADC and SCK pins, the LTC2404/LTC2408 offer two modes of operation: internal or external SCK. These modes do not require program- ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock A major advantage delta-sigma converters offer over conventional type converters is an on-chip digital filter (commonly known as Sinc or Comb filter). For high resolution, low frequency applications, this filter is typi- cally designed to reject line frequencies of 50 or 60Hz plus their harmonics. In order to reject these frequencies in excess of 110dB, a highly accurate conversion clock is required. The LTC2404/LTC2408 incorporate an on-chip highly accurate oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2404/ LTC2408 reject line frequencies (50 or 60Hz ±2%) a minimum of 110dB. APPLICATIONS INFORMATION Figure 1. LTC2408 State Transition Diagram CONVERT SLEEP CHANNEL SELECT (SLEEP) DATA OUTPUT (CHANNEL SELECT) 24048 F01 0 1 CSADC AND SCK |
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