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LTC2428I Datasheet(PDF) 16 Page - Linear Technology |
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LTC2428I Datasheet(HTML) 16 Page - Linear Technology |
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16 / 28 page  16 LTC2424/LTC2428 APPLICATIONS INFORMATION In addition, the CSADC signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2424/LTC2428 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CSADC pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs with CSADC = 0). Multiplexer Chip Select (CSMUX) For 4-wire operation, this pin is tied directly to CSADC or the output of an inverter tied to CSADC. CSMUX (Pin 20) is driven HIGH during selection of a multiplexer channel. On the falling edge of CSMUX, the selected channel is enabled and drives MUXOUT. Data Input (DIN) The data input to the multiplexer, DIN (Pin 21), is used to program the multiplexer. The input channel is selected by serially shifting a 4-bit input word into the DIN pin under the control of the multiplexer clock, CLK. Data is shifted into the multiplexer on the rising edge of CLK. Table 3 shows the logic table for channel selection. In order to select or change a previously programmed channel, an enable bit (DIN = 1) must proceed the 3-bit channel select serial data. The user may set DIN = 0 to continually convert on the previously selected channel. SERIAL INTERFACE TIMING MODES The LTC2424/LTC2428’s 4-wire interface is SPI and MICROWIRE compatible. This interface offers two modes of operation. These include an internal or external serial clock. The following sections describe both of these serial interface timing modes in detail. For both cases the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 5 for a summary. External Serial Clock (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock (SCK) to shift out the conversion result, see Figure 13. This same external clock signal drives the CLK pin in order to pro- gram the multiplexer. A single CS signal drives both the multiplexer CSMUX and converter CSADC inputs. This common signal is used to monitor and control the state of the conversion as well as enable the channel selection. The serial clock mode is selected on the falling edge of CSADC. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CSADC falling edge. The serial data output pin (SDO) is HI-Z as long as CSADC is HIGH. At any time during the conversion cycle, CSADC may be pulled LOW in order to monitor the state of the converter. While CSADC is LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CSADC, the device automatically enters the low power sleep state once the conversion is complete. While the device is in the sleep state, prior to entering the data output state, the user may program the multiplexer. As shown in Figure 13, the multiplexer channel is selected by serial shifting a 4-bit word into the DIN pin on the rising edge of CLK (CLK is tied to SCK). The first bit is an enable bit that must be HIGH in order to program a channel. The next three bits determine which channel is selected, see Table 3. On the falling edge of CSMUX, the new channel is selected and will be valid for the first conversion performed following the data output state. Clock signals applied to the CLK pin while CSMUX is LOW (during the data output state) will have no effect on the channel selection. Further- more, if DIN is held LOW or CLK is held LOW during the sleep state, the channel selection is unchanged. When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. Table 5. LTC2424/LTC2428 Interface Timing Modes Conversion Data Connection SCK Cycle Output and Configuration Source Control Control Waveforms External SCK External CSADC and SCK CSADC and SCK Figures 7, 8, 9 Internal SCK Internal CSADC ↓ CSADC ↓ Figures 10, 11 |
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