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LTC2404CG Datasheet(PDF) 30 Page - Linear Technology

Part # LTC2404CG
Description  4-/8-Channel 24-Bit uPower No Latency ADCs
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2404CG Datasheet(HTML) 30 Page - Linear Technology

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30
LTC2404/LTC2408
APPLICATIONS INFORMATION
DIN1
EQU
$00
This memory location holds the LTC2408’s bits 31 - 24
DIN2
EQU
$01
This memory location holds the LTC2408’s bits 23 - 16
DIN3
EQU
$02
This memory location holds the LTC2408’s bits 15 - 08
DIN4
EQU
$03
This memory location holds the LTC2408’s bits 07 - 00
MUX
EQU
$04
This memory location holds the MUX address data
*
***************************************
* Start GETDATA Routine
*
***************************************
*
ORG
$C000
Program start location
*
LDS
$CFFF
Top of C page RAM, beginning location of stack
INIT1
LDAA
#$2F
-,-,1,0;1,1,1,1
*
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA
PORTD
Keeps SS* a logic high when DDRD, bit 5 is set
LDAA
#$38
-,-,1,1;1,0,0,0
STAA
DDRD
SS* , SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
* DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA
#$50
STAA
SPCR
The SPI is configured as Master, CPHA = 0, CPOL = 0
*
and the clock rate is E/2
*
(This assumes an E-Clock frequency of 4MHz. For higher
*
E-Clock frequencies, change the above value of $50 to a
*
value that ensures the SCK frequency is 2MHz or less.)
GETDATA PSHX
PSHY
PSHA
LDX
#$0
The X register is used as a pointer to the memory
*
locations that hold the conversion data
LDY
#$1000
*
*******************************
* The next routine sends data to the *
* LTC2408 an sets its MUX channel
*
*******************************
*
LDAA
$MUX
Retrieve MUX address
ORAA
#$08
Set the MUX’s ENABLE bit
STAA
SPDR
Transfer Accum. A contents to SPI register to initiate
*
serial transfer
WAITMUX LDAA
SPSR
Get SPI transfer status
BPL
WAITMUX If the transfer is not finished, read status
*
***************************************
* Enable the LTC2408
*
***************************************
*
BCLR
PORTD,Y %00100000 This sets the SS* output bit to a logic
*
low, selecting the LTC2408
*
***************************************
* The next short loop waits for the
*
* LTC2408’s conversion to finish before
*
* starting the SPI data transfer
*
***************************************
*
CONVEND LDAA
PORTD
Retrieve the contents of port D
ANDA
#%00000100
Look at bit 2
*
Bit 2 = Hi; the LTC2408’s conversion is not
*
complete
*
Bit 2 = Lo; the LTC2408’s conversion is complete
BNE
CONVEND
Branch to the loop’s beginning while bit 2 remains
*
high


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