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LTC2400C Datasheet(PDF) 11 Page - Linear Technology |
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LTC2400C Datasheet(HTML) 11 Page - Linear Technology |
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11 / 40 page  11 LTC2400 APPLICATIONS INFORMATION 2400 F02 VCC + 0.3V 9/8VREF VREF 1/2VREF –0.3V –1/8VREF 0 NORMAL INPUT RANGE EXTENDED INPUT RANGE ABSOLUTE MAXIMUM INPUT RANGE Figure 2. LTC2400 Input Range For large values of VREF this range is limited by the absolute maximum voltage range of – 0.3V to (VCC + 0.3V). Beyond this range the input ESD protection devices begin to turn on and the errors due to the input leakage current increase rapidly. Input signals applied to VIN may extend below ground by – 300mV and above VCC by 300mV. In order to limit any fault current, a resistor of up to 5k may be added in series with the VIN pin without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between this series resistance and the VIN pin as low as possible; therefore, the resistor should be located as close as practical to the VIN pin. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Analog Input/Reference Current section. In addition a series resistor will introduce a temperature dependent offset error due to the input leak- age current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2400 serial output data stream is 32 bits long. The first 4 bits represent status information indicating the sign, input range and conversion state. The next 24 bits are the conversion result, MSB first. The remaining 4 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indi- cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. The sign bit changes state during the zero code. Bit 28 (forth output bit) is the extended input range (EXR) indicator. If the input is within the normal input range 0 ≤ VIN ≤ VREF, this bit is LOW. If the input is outside the normal input range, VIN > VREF or VIN < 0, this bit is HIGH. The function of these bits is summarized in Table 1. Table 1. LTC2400 Status Bits Bit 31 Bit 30 Bit 29 Bit 28 Input Range EOC DMY SIG EXR VIN > VREF 0 011 0 < VIN ≤ VREF 0 010 VIN = 0+/0– 0 0 1/0 0 VIN < 0 0 001 Bit 27 (fifth output bit) is the most significant bit (MSB). Bits 27-4 are the 24-bit conversion result MSB first. Bit 4 is the least significant bit (LSB). Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may be included in averaging or discarded without loss of resolution. Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance and any SCK clock pulses are ignored by the internal data out shift register. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted |
Similar Part No. - LTC2400C |
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Similar Description - LTC2400C |
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