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LTC1929I Datasheet(PDF) 9 Page - Linear Technology |
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LTC1929I Datasheet(HTML) 9 Page - Linear Technology |
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9 / 24 page  9 LTC1929 but it is very dependent on inductance selected. As induc- tance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that induc- tance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manu- facturer is Kool M µ. Toroids are very space efficient, especially when you can use several layers of wire. Be- cause they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly. Power MOSFET, D1 and D2 Selection Two external power MOSFETs must be selected for each controller with the LTC1929: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC volt- age. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level thresh- old MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sublogic-level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specifi- cation for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage, and maximum output current. When the LTC1929 is operating in continuous mode the duty factors for the top and bottom MOSFETs of each output stage are given by: Main Switch Duty Cycle V V OUT IN = Synchronous Switch Duty Cycle VV V IN OUT IN = – The MOSFET power dissipations at maximum output current are given by: P V V I R kV I Cf MAIN OUT IN MAX DS ON IN MAX RSS = + () + () ()( ) 2 1 2 2 2 δ () P VV V I R SYNC IN OUT IN MAX DS ON = + () – () 2 1 2 δ where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses but the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actual provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs. Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOS- FET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diodes, D1 and D2 shown in Figure 1 conduct during the dead-time between the conduction of the two large power MOSFETs. This helps prevent the body diode APPLICATIO S I FOR ATIO |
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