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LTC1736IG Datasheet(PDF) 7 Page - Linear Technology |
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LTC1736IG Datasheet(HTML) 7 Page - Linear Technology |
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7 / 28 page  7 LTC1736 PI FU CTIO S COSC (Pin 1): External capacitor COSC from this pin to ground sets the operating frequency. RUN/SS (Pin 2): Combination of Soft-Start and Run Control Inputs. A capacitor to ground at this pin sets the ramp time to full output current. The time is approximately 1.25s/ µF. Forcing this pin below 1.5V causes the device to be shut down. In shutdown all functions are disabled. Latchoff overcurrent protection is also invoked via this pin as described in the Applications Information section. ITH (Pin 3): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 2.4V. FCB (Pin 4): Forced Continuous/Synchronization Input. Tie this pin to ground for continuous synchronous opera- tion, to a resistive divider from the secondary output when using a secondary winding, or to INTVCC to enable Burst Mode operation at low load currents. Clocking this pin with a signal above 1.5VP-P disables Burst Mode operation but allows cycle skipping at low load currents and synchro- nizes the internal oscillator with the external clock. SGND (Pin 5): Small-Signal Ground. All small-signal components such as COSC, CSS plus the loop compensa- tion resistors and capacitor(s) should single-point tie to this pin. This pin should, in turn, connect to PGND. PGOOD (Pin 6): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on the VOSENSE pin is not within ±7.5% of its set point. SENSE – (Pin 7): The (–) Input to the Current Comparator. SENSE + (Pin 8): The (+) Input to the Current Comparator. Built-in offsets between SENSE – and SENSE + pins in conjunction with RSENSE set the current trip threshold. VFB (Pin 9): Divided Down VOSENSE Voltage Feeding the Error Amplifier of the Regulator. The VID inputs program a resistive divider between VOSENSE and SGND; the tap point on the divider is VFB . The voltage on VFBis 0.8V when the output is in regulation. This pin can be bypassed to SGND with 50pF to 100pF. VOSENSE (Pin 10): Receives the remotely sensed feedback voltage from the output. VID0 to VID4 (Pins 11 to 15): Digital Inputs for controlling the output voltage from 0.925V to 2.0V. Table 1 specifies the VOSENSE voltages for the 32 combinations of digital inputs. The LSB (VID0) represents 50mV increments in the upper voltage range (2.00V to 1.30V) and 25mV increments in the lower voltage range (1.275V to 0.925V). Logic Low = GND, Logic High = VIDVCC or Float. VIDVCC (Pin 16): VID Input Supply Voltage. Can range from 2.7V to 7V. Typically this pin is tied to INTVCC. EXTVCC (Pin 17): Input to the Internal Switch Connected to INTVCC. This switch closes and supplies VCC power whenever EXTVCC is higher than 4.7V. See EXTVCC con- nection in the Applications Information section. Do not exceed 7V to this pin and ensure EXTVCC ≤ VIN. PGND (Pin 18): Driver Power Ground. This pin connects to the source of the bottom N-channel MOSFET, the anode of the Schottky diode and the (–) terminal of CIN. BG (Pin 19): High Current Gate Drive for Bottom N-Channel MOSFET. Voltage swing at this pin is from ground to INTVCC . INTVCC (Pin 20): Output of the Internal 5.2V Regulator and EXTVCC Switch. The driver and control circuits are pow- ered from this voltage. Decouple to power ground with a 1 µF ceramic capacitor placed directly adjacent to the IC together with a minimum of 4.7 µF tantalum or other low ESR capacitor. VIN (Pin 21): Main Supply Pin. This pin must be closely decoupled to power ground. SW (Pin 22): Switch Node Connection to Inductor and Bootstrap Capacitor. Voltage swing at this pin is from a Schottky diode (external) voltage drop below ground to VIN. BOOST (Pin 23): Supply to Topside Floating Driver. The bootstrap capacitor is returned to this pin. Voltage swing at this pin is from a diode drop below INTVCC to VIN + INTVCC. TG (Pin 24): High Current Gate Drive for Top N-Channel MOSFET. This is the output of a floating driver with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. |
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