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LTC1596AIN Datasheet(PDF) 4 Page - Linear Technology

Part # LTC1596AIN
Description  Serial 16-Bit Multiplying DACs
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1596AIN Datasheet(HTML) 4 Page - Linear Technology

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LTC1595/LTC1596/LTC1596-1
ELECTRICAL CHARACTERISTICS
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
The q denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale.
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: IOUT1 with DAC register loaded with all 0s.
Note 6: Typical temperature coefficient is 100ppm/C.
Note 7: OUT1 load = 100
Ω in parallel with 13pF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSRI
Serial Input Data Pulse Width
q
60
ns
tCH
Clock Pulse Width High
q
60
ns
tCL
Clock Pulse Width Low
q
60
ns
tLD
Load Pulse Width
q
60
ns
tASB
LSB Clocked into Input Register
q
0ns
to DAC Register Load Time
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics (LTC1596/LTC1596-1)
tDS1
Serial Input to Strobe Setup Time
STB1 Used as the Strobe
q
30
5
ns
tDS2
STB2 Used as the Strobe
q
20
– 5
ns
tDS3
STB3 Used as the Strobe
q
25
0
ns
tDS4
STB4 Used as the Strobe
q
20
– 5
ns
tDH1
Serial Input to Strobe Hold Time
STB1 Used as the Strobe
q
30
5
ns
tDH2
STB2 Used as the Strobe
q
40
15
ns
tDH3
STB3 Used as the Strobe
q
35
10
ns
tDH4
STB4 Used as the Strobe
q
40
15
ns
tSRI
Serial Input Data Pulse Width
q
60
ns
tSTB1 to
Strobe Pulse Width
(Note 11)
q
60
ns
tSTB4
tSTB1 to
Strobe Pulse Width
(Note 12)
q
60
ns
tSTB4
tLD1, tLD2
LD Pulse Width
q
60
ns
tASB
LSB Strobed into Input Register
q
0ns
to Load DAC Register Time
tCLR
Clear Pulse Width
q
100
ns
tPD1
STB1 to SRO Propagation Delay
CL = 50pF
q
30
150
ns
tPD
STB2, STB3, STB4 to SRO
CL = 50pF
q
30
200
ns
Propagation Delay
Power Supply
VDD
Supply Voltage
q
4.5
5
5.5
V
IDD
Supply Current
Digital Inputs = 0V or VDD
q
1.5
10
µA
Note 8: To 0.0015% for a full-scale change, measured from the falling
edge of LD1, LD2 or LD.
Note 9: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s;
op amp = LT1007.
Note 10: Calculation from en = √4kTRB where: k = Boltzmann constant
(J/
°K); R = resistance (Ω); T = temperature (°K); B = bandwidth (Hz).
Note 11: Minimum high time for STB1, STB2, STB4. Minimum low time
for STB3.
Note 12: Minimum low time for STB1, STB2, STB4. Minimum high time
for STB3.


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