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LTC1657IN Datasheet(PDF) 8 Page - Linear Technology |
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LTC1657IN Datasheet(HTML) 8 Page - Linear Technology |
8 / 12 page 8 LTC1657 Parallel Interface The data on the input of the DAC is written into the DAC’s input registers when Chip Select (CSLSB and/or CSMSB) and WR are at a logic low. The data that is written into the input registers will depend on which of the Chip Selects are at a logic low (see Digital Interface Truth Table). If WR and CSLSB are both low and CSMSB is high, then only data on the eight LSBs (D0 to D7) is written into the input registers. Similarly, if WR and CSMSB are both low and CSLSB is high, then only data on the eight MSBs (D8 to D15) is written into the input registers. Data is written into both the Least Significant Data Bits (D0 to D7) and the Most Significant Bits (D8 to D15) at the same time if WR, CSLSB and CSMSB are low. If WR is high or both CSMSB and CSLSB are high, then no data is written into the input registers. Once data is written into the input registers, it can be written into the DAC register. This will update the analog voltage output of the DAC. The DAC register is written by a logic low on LDAC. The data in the DAC register will be held when LDAC is high. When WR, CSLSB, CSMSB and LDAC are all low, the registers are transparent and data on pins D0 to D15 flows directly into the DAC register. For an 8-bit data bus connection, tie the MSB byte data pins to their corresponding LSB byte pins (D15 to D7, D14 to D6, etc). Power-On Reset The LTC1657 has an internal power-on reset that resets all internal registers to 0’s on power-up (equivalent to the CLR pin function). Reference The LTC1657 includes an internal 2.048V reference, giv- ing the LTC1657 a full-scale range of 4.096V in the gain- of-2 configuration. The onboard reference in the LTC1657 is not internally connected to the DAC’s reference resistor string but is provided on an adjacent pin for flexibility. Because the internal reference is not internally connected OPERATION to the DAC resistor ladder, an external reference can be used or the resistor ladder can be driven by an external source in multiplying applications. The external reference or source must be capable of driving the 16k (minimum) DAC ladder resistance. Internal reference output noise can be reduced with a bypass capacitor to ground. (Note: The reference does not require a bypass capacitor to ground for nominal opera- tion.) When bypassing the reference, a small value resistor in series with the capacitor is recommended to help reduce peaking on the output. A 10 Ωresistorinserieswitha4.7µF capacitor is optimum for reducing reference generated noise. Internal reference output voltage noise spectral density at 1kHz is typically 150nV/ √Hz. DAC Resistor Ladder The high and low end of the DAC ladder resistor string (REFHI and REFLO, respectively) are not connected inter- nally on this part. Typically, REFHI will be connected to REFOUT and REFLO will be connected to GND. X1/X2 connected to GND will give the LTC1657 a full-scale output swing of 4.096V. Either of these pins can be driven up to VCC – 1.5V when using the buffer in the gain-of-1 configuration. The resistor string pins can be driven to VCC/2 when the buffer is in the gain of 2 configuration. The resistance between these two pins is typically 25k (16k min). Voltage Output The output buffer for the LTC1657 can be configured for two different gain settings. By tying the X1/X2 pin to GND, the gain is set to 2. By tying the X1/X2 pin to VOUT, the gain is set to unity. The LTC1657 rail-to-rail buffered output can source or sink 5mA within 500mV of the positive supply voltage or ground at room temperature. The output stage is equipped with a deglitcher that results in a midscale glitch impulse of 8nV • s. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40 Ω when driving a load to the rails. |
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