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LTC1657C Datasheet(PDF) 5 Page - Linear Technology |
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LTC1657C Datasheet(HTML) 5 Page - Linear Technology |
5 / 12 page 5 LTC1657 WR (Pin 1): Write Input (Active Low). Used with CSMSB and/or CSLSB to control the input registers. While WR and CSMSB and/or CSLSB are held low, data writes into the input register. CSLSB (Pin 2): Chip Select Least Significant Byte (Active Low). Used with WR to control the LSB 8-bit input regis- ters. While WR and CSLSB are held low, the LSB byte writes into the LSB input register. Can be connected to CSMSB for simultaneous loading of both sets of input latches on a 16-bit bus. CSMSB (Pin 3): Chip Select Most Significant Byte (Active Low). Used with WR to control the MSB 8-bit input registers. While WR and CSMSB are held low, the MSB byte writes into the MSB input register. Can be connected to CSLSB for simultaneous loading of both sets of input latches on a 16-bit bus. D0 to D7 (Pins 4 to 11): Input data for the Least Significant Byte. Written into LSB input register when WR = 0 and CSLSB = 0. D8 to D15 (Pins 12 to 19): Input data for the Most Signifi- cant Byte. Written into MSB input register when WR = 0 and CSMSB = 0. GND (Pin 20): Ground. REFLO (Pin 21): Lower input terminal of the DAC’s inter- nal resistor ladder. Typically connected to Analog Ground. An input code of (0000)H will connect the positive input of PIN FUNCTIONS the output buffer to this end of the ladder. Can be used to offset the zero scale above ground. REFHI (Pin 22): Upper input terminal of the DAC’s internal resistor ladder. Typically connected to REFOUT. An input code of (FFFF)H will connect the positive input of the output buffer to 1LSB below this voltage. REFOUT (Pin 23): Output of the internal 2.048V reference. Typically connected to REFHI to drive internal DAC resistor ladder. VCC (Pin 24): Positive Power Supply Input. 4.5V ≤ VCC ≤ 5.5V. Requires a 0.1 µF bypass capacitor to ground. VOUT (Pin 25): Buffered DAC Output. X1/X2 (Pin 26): Gain Setting Resistor Pin. Connect to GND for G = 2 or to VOUT for G = 1. This pin should always be tied to a low impedance source, such as ground or VOUT, to ensure stability of the output buffer when driving capacitive loads. CLR (Pin 27): Clear Input (Asynchronous Active Low). A low on this pin asynchronously resets all input and DAC registers to 0s. LDAC (Pin 28): Load DAC (Asynchronous Active Low). Used to asynchronously transfer the contents of the input registers to the DAC register which updates the output voltage. If held low, the DAC register loads data from the input registers which will immediately update VOUT. |
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