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LTC1599AIG Datasheet(PDF) 9 Page - Linear Technology |
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LTC1599AIG Datasheet(HTML) 9 Page - Linear Technology |
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9 / 20 page  9 LTC1599 APPLICATIONS INFORMATION Description The LTC1599 is a 16-bit multiplying, current output DAC with a 2-byte (8-bit wide) digital interface. The device operates from a single 5V supply and provides both unipolar 0V to – 10V or 0V to 10V and bipolar ±10V output ranges from a 10V or –10V reference input. It has three additional precision resistors on chip for bipolar opera- tion. Refer to the Block Diagram regarding the following description. The 16-bit DAC consists of a precision R-2R ladder for the 13LSBs. The 3MSBs are decoded into seven segments of resistor value R (48k typ). Each of these segments and the R-2R ladder carries an equally weighted current of one eighth of full scale. The feedback resistor RFB and 4-quadrant resistor ROFS have a value of R/4. 4-quadrant resistors R1 and R2 have a magnitude of R/4. R1 and R2 together with an external op amp (see Figure 4) inverts the reference input voltage and applies it to the 16-bit DAC input REF, in 4-quadrant operation. The REF pin presents a constant input impedance of R/8 in unipolar mode and R/12 in bipolar mode. The output impedance of the current output pin IOUT1 varies with DAC input code. The IOUT1 capacitance due to the NMOS current steering switches also varies with input code from 70pF to 115pF. IOUT2F and IOUT2S are normally tied to the system analog ground. An added feature of the LTC1599 is a proprietary deglitcher that reduces glitch impulse to 1.5nV-s over the DAC output voltage range. Digital Section The LTC1599 has a byte wide (8-bit), digital input data bus. The device is double-buffered with two 16-bit registers. The double-buffered feature permits the update of several DACs simultaneously. The input register is loaded directly from an 8-bit (or higher) microprocessor bus in a two step sequence. The MLBYTE pin selects whether the 8 input data bits are loaded into the LSB or the MSB byte of the input register. When MLBYTE is brought to a logic low level and WR is given a logic low going pulse, the 8 data bits are loaded into the LSB byte of the input register. Conversely, when MLBYTE is brought to a logic high level and WR is given a logic low going pulse, the 8 data bits are loaded into the MSB byte of the input register. If WR is brought to a logic low level, the existing level of MLBYTE determines which byte is loaded into the input register. If the logic level of MLBYTE is changed while WR remains low, no change will occur. This is because WR is an edge triggered signal and once it goes low it locks out any further changes in MLBYTE. WR must be brought high and then low again to accept the new MLBYTE condition. The second register (DAC register) is updated with the data from the input register when the LD pin is brought to a logic low level. Updating the DAC register updates the DAC output with the new data. The deglitcher is activated on the falling edge of the LD pin. The asynchronous clear pin resets the LTC1599 to zero scale when the CLVL pin is at a logic low level and to midscale when the CLVL pin is at a logic high level. CLR resets both the input and DAC registers. The device also has a power-on reset. Table 1 shows the truth table for the device. Unipolar Mode (2-Quadrant Multiplying, VOUT = 0V to – VREF) The LTC1599 can be used with a single op amp to provide 2-quadrant multiplying operation as shown in Figure 1. With a fixed – 10V reference, the circuit shown gives a precision unipolar 0V to 10V output swing. Bipolar Mode (4-Quadrant Multiplying, VOUT = – VREF to VREF) The LTC1599 contains on chip all the 4-quadrant resistors necessary for bipolar operation. 4-quadrant multiplying operation can be achieved with a minimum of external components, a capacitor and a dual op amp, as shown in Figure 3. With a fixed 10V reference, the circuit shown gives a precision bipolar – 10V to 10V output swing. Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC1599, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 2 and 3 contain equations for evaluating the effects of op amp parameters on the LTC1599’s accuracy when |
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