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LTC1553 Datasheet(PDF) 10 Page - Linear Technology |
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LTC1553 Datasheet(HTML) 10 Page - Linear Technology |
10 / 24 page 10 LTC1553 APPLICATIONS INFORMATION OVERVIEW The LTC1553 is a voltage feedback, synchronous switch- ing regulator controller (see Block Diagram) designed for use in high power, low voltage step-down (buck) convert- ers. It is designed to satisfy the requirements of the Intel Pentium II power supply specification. It includes an on-chip DAC to control the output voltage, a PWM genera- tor, a precision reference trimmed to ±1%,twohighpower MOSFET gate drivers and all the necessary feedback and control circuitry to form a complete switching regulator circuit. The LTC1553 includes a current limit sensing circuit that uses the upper external power MOSFET as a current sensing element, eliminating the need for an external sense resistor. Once the current comparator, CC, detects an overcurrent condition, the duty cycle is reduced by discharging the soft start capacitor through a voltage- controlled current source. Under severe overloads or output short circuit conditions, the chip will be repeatedly forced into soft start until the short is removed, preventing the external components from being damaged. Under output overvoltage conditions, the MOSFET drivers will be disabled permanently until the chip power supply is recycled or the OUTEN pin is toggled. OUTEN can optionally be connected to an external nega- tive temperature coefficient (NTC) thermistor placed near the external MOSFETs or the microprocessor. Three thresh- old levels are provided internally. When OUTEN drops to 2V, OT will trip, issuing a warning to the external CPU. If the temperature continues to rise and the OUTEN input drops to 1.7V, the G1 and G2 pins will be forced low. If OUTEN is pulled below 1.2V, the LTC1553 will go into shutdown mode, cutting the supply current to a minimum. If thermal shutdown is not required, OUTEN can be con- nected to a conventional TTL enable signal. The free- running 300kHz PWM frequency can be synchronized to a faster external clock connected to OUTEN. Adjusting the oscillator frequency can add flexibility in the external component selection. See the Clock Synchronization section. Output regulation can be monitored with the PWRGD pin which in turn monitors the internal MIN and MAX com- parators. If the output is ±5% beyond the selected value for more than 500 µs, the PWRGD output will be pulled low. Once the output has settled within ±5% of the selected value for more than 1ms, PWRGD will return high. THEORY OF OPERATION Primary Feedback Loop The regulator output voltage at the SENSE pin is divided down internally by a resistor divider with a total resistance of approximately 120k Ω. This divided down voltage is subtracted from a reference voltage supplied by the DAC output. The resulting error voltage is amplified by the error amplifier and the output is compared to the oscillator ramp waveform by the PWM comparator. This PWM signal controls the external MOSFETs through G1 and G2. The resulting chopped waveform is filtered by LO and COUT closing the loop. Loop frequency compensation is achieved with an external RC + C network at the COMP pin, which is connected to the output node of the transconductance amplifier. MIN, MAX Feedback Loops Two additional comparators in the feedback loop provide high speed fault correction in situations where the ERR amplifier may not respond quickly enough. MIN compares the feedback signal FB to a voltage 60mV (5%) below the internal reference. If FB is lower than the threshold of this comparator, the MIN comparator overrides the ERR amplifier and forces the loop to full duty cycle which is set by the internal oscillator typically to 84%. Similarly, the MAX comparator forces the output to 0% duty cycle if FB is more than 5% above the internal reference. To prevent these two comparators from triggering due to noise, the MIN and MAX comparators’ response times are deliber- ately controlled so that they take two to three microsec- onds to respond. These two comparators help prevent extreme output perturbations with fast output transients, while allowing the main feedback loop to be optimally compensated for stability. |
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