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LTC1536CS8 Datasheet(PDF) 6 Page - Linear Technology |
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LTC1536CS8 Datasheet(HTML) 6 Page - Linear Technology |
6 / 12 page 6 LTC1536 PIN FUNCTIONS VCC3 (Pin 1): 3.3V Sense Input and Power Supply Pin for the IC. Bypass to ground with ≥0.1µF ceramic capacitor. VCC5 (Pin 2): 5V Sense Input. Used as gate drive for RST output FET when the voltage on VCC5 is greater than the voltage on VCC3. VCCA (Pin 3): 1V Sense, High Impedance Input. Can be used as a logic input with a 1V threshold. If unused it can be tied to either VCC3 or VCC5. GND (Pin 4): Ground. RST (Pin 5): Reset Logic Output. Active high CMOS logic output, drives high to VCC3, buffered compliment of RST. An external pull-down on the RST pin will drive this pin high. RST (Pin 6): Reset Logic Output. Active low, open-drain logic output with weak pull-up to VCC3. Can be pulled up greater than VCC3 when interfacing to 5V logic. VCC3 SOFT RESET RESET 3 VCCA 2 VCC5 TO POWER DETECT 8 PBR 7 SRST 4 GND REF PBR TIMER 200ms RESET GENERATOR POWER DETECT/ GATE DRIVE VCC3 6 RST 5 VCC3 VCC3 VCC5 RST 6 µA VCC3 7 µA 6 µA FAST FAST SLOW FAST SLOW SLOW 1 VCC3 TO POWER DETECT AND VCC INTERNAL 1326 BD BLOCK DIAGRAM Asserted when one or more of the supplies are below trip thresholds and held for 200ms after all supplies become valid. Also asserted after PBR is held low for more than two seconds and for an additional 200ms after PBR is released. SRST (Pin 7): “Soft” Reset. Active low, open-drain logic output with weak pull-up to VCC3. Can be pulled up greater than VCC3 when interfacing to 5V logic. Asserted for 100µs after PBR is held low for less than two seconds and released. PBR (Pin 8): Pushbutton Reset. Active low logic input with weak pull-up to VCC3. Can be pulled up greater than VCC3 when interfacing to 5V logic. When asserted for less than two seconds, outputs a soft reset 100 µspulseontheSRST pin. When PBR is asserted for greater than two seconds, the RST output is forced low and remains low until 200ms after PBR is released. |
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