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LTC1456 Datasheet(PDF) 5 Page - Linear Technology |
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LTC1456 Datasheet(HTML) 5 Page - Linear Technology |
5 / 8 page 5 LTC1456 CLK (Pin 1): The Serial Interface Clock. Internal Schmitt trigger on this input allows direct optocoupler interface. DIN (Pin 2): The Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. CS/LD (Pin 3): The Serial Interface Enable and Load Control. When CS/LD is low the CLK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. When CS/LD is high the CLK is disabled internally. PIN FUNCTIONS DOUT (Pin 4): The Output of the Shift Register Which Becomes Valid on the Rising Edge of the Serial Clock. GND (Pin 5): Ground. CLR (Pin 6): The Clear Input. When pulled low, this pin asynchronously clears the internal shift and DAC registers to zero scale. Should be tied high for normal operation. VOUT (Pin 7): The Buffered DAC Output. VCC (Pin 8): The Positive Supply Input. 4.5V ≤ VCC ≤ 5.5V. Requires a bypass capacitor to ground. B11 MSB B10 t1 t9 B1 t6 B0 LSB B11 CURRENT WORD t7 t2 t4 t3 t8 CLK DIN DOUT CS/LD t5 1456 TD B0 PREVIOUS WORD B11 PREVIOUS WORD B10 B1 B0 I DAGRA BLOCK DAC REGISTER LD 12-BIT SHIFT REGISTER POWER-ON RESET 1146 BD CLK 1 DIN 2 DOUT 4 VOUT 7 CLR 6 GND 5 VCC 8 3 CS/LD 12-BIT DAC 2.048V + – TI I G DIAGRA |
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