6

LTC1448

DEFI ITIO S

OPERATIO

Differential Nonlinearity (DNL): The differerence

between the measured change and the ideal 1LSB change

for any two adjacent codes. The DNL error between any

two codes is calculated as follows:

DNL = (

where

two adjacent codes.

Digital Feedthrough: The glitch that appears at the analog

output caused by AC coupling from the digital inputs when

they change state. The area of the glitch is specified in

(nV)(sec).

Full-Scale Error (FSE): The deviation of the actual full-

scale voltage from ideal. FSE includes the effects of offset

and gain errors (see Applications Information).

Integral Nonlinearity (INL): The deviation from a straight

line passing through the endpoints of the DAC transfer

curve (Endpoint INL). Because the output cannot go below

zero, the linearity is measured between full scale and the

lowest code which guarantees the output will be greater

while pulling to within 300mV of the positive supply

voltage or ground. The output swings to within a few

millivolts of either supply rail when unloaded and has an

equivalent output resistance of 30

Ω when driving a load to

the rails. The output can drive 1000pF without going into

oscillation.

The output swings from 0V to the voltage at the REF pin,

than zero. The INL error at a given input code is calculated

as follows:

the given input code.

Least Significant Bit (LSB): The ideal voltage difference

between two successive codes.

Resolution (n): Defines the number of DAC output states

imply linearity.

output when the DAC is loaded with all zeros. A single

supply DAC can have a true negative offset, but the output

cannot go below zero (see Applications Information).

For this reason, single supply DAC offset is measured at

the lowest code that guarantees the output will be greater

than zero.

Serial Interface

The data on the DIN input is loaded into the shift register

on the rising edge of the clock. Data is loaded as one 24-

bit word where the first 12 bits are for DAC A and the

second 12 are for DAC B. For each 12-bit segment the MSB

is loaded first. Data from the shift register is loaded into the

DAC register when CS/LD is pulled high. The clock is

disabled internally when CS/LD is high. Note: CLK must be

low before CS/LD is pulled low to avoid an extra internal

clock pulse.

Voltage Output

The LTC1448’s rail-to-rail buffered outputs can source or

sink 5mA over the entire operating temperature range