Electronic Components Datasheet Search |
|
UPD75P238 Datasheet(PDF) 31 Page - NEC |
|
UPD75P238 Datasheet(HTML) 31 Page - NEC |
31 / 50 page 31 µPD75P238 *1. CPU clock ( Φ) cycle time is determined by the oscillator for frequency of the connected oscil- lator, the system clock control register (SCC) and processor clock control register (PCC). The cycle time tCY characteristics for supply voltage VDD when the main system clock is in operation is shown on the right. 2. 2tCY or 128/fX is set by interrupt mode register (IM0) setting. AC CHARACTERISTICS (Ta = –40 to +70 °C, VDD = 2.7 to 6.0 V) (1) Basic Operation PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Operation with VDD = 4.75 0.67 64 µs main system to 6.0 V clock 2.6 64 µs Operation with subsystem clock 114 122 125 µs VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz VDD = 4.5 to 6.0 V 0.48 µs 1.8 µs Interrupt input high INT0 *2 µs and low-level widths INT1, 2, 4 10 µs RESET low level 10 µs widths tCY fTI tTIH, tTIL tRSL tINTH, tINTL TI0 input high and low-level widths tcy vs VDD (When main system clock is in operation) Power Supply Voltage VDD [V] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 60 64 70 6 Operation Guaranteed Range TI0 input frequency CPU clock cycle time (minimum instruction execution time = one machine cycle)*1 |
Similar Part No. - UPD75P238 |
|
Similar Description - UPD75P238 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |