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UPD75P238 Datasheet(PDF) 29 Page - NEC |
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UPD75P238 Datasheet(HTML) 29 Page - NEC |
29 / 50 page 29 µPD75P238 DC CHARACTERISTICS (Ta = –40 to +70 °C, VDD = 2.7 to 6.0 V) (2/3) Output leakage current high Output leakage current low Display output current On-chip pull-up resistor Power supply current*1 VOUT = VDD 3 µA VDD = 4.5 to 6.0 V VOD = VDD – 2 V Display output Operat- ing mode HALT mode Operat- ing mode HALT mode ILOH1 ILOL2 IOD ILOL1 RL RV1 IDDI IDD2 IDDI IDD2 PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT All ports and pins except those listed below. ILOH2 Port 4, 5 VOUT = 10 V 20 µA All ports and pins except those listed below. Display VOUT = VLOAD = –10 µA output VDD – 35 V S0 to S9, –3 –5.5 mA S16 to S23 T0 to T15 –15 –22 mA On-chip pull-down resistor VOD – VLOAD = 35 V 25 50 135 k Ω (Mask option) Port 0, 1, 2, 3, VDD = 5 V ± 10% 15 40 80 k Ω 6 (Except P00) VIN = 0 V VDD = 3 V ± 10% 30 300 k Ω VDD = 5V 918 mA ±10%*2 VDD = 3 V 13 mA ±10%*3 VDD = 5 V 900 2700 µA ±10% VDD = 3 V 300 900 µA ±10% VDD = 5 V 515 mA ±10%*2 VDD = 3 V 0.9 2.7 mA ±10%*3 VDD = 5 V 600 1800 µA ±10% VDD = 3 V 200 600 µA ±10% *1. Current to the on-chip pull-down resistor (pull-up) and power-on reset circuit (mask option) is not included. 2. When the processor clock control register (PCC) is set to 0011 and is operated at high-speed mode. 3. When the PCC register is set to 0000 and is operated in the low-speed mode. 4. Includes the case where the subsystem clock oscillating. VOUT = 0 V –3 µA 6MHz crystal oscillation C1 = C2 = 22 pF*4 4.19MHz crystal oscillation C1 = C2 = 22 pF*4 |
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Similar Description - UPD75P238 |
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