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LTC1417AIGN Datasheet(PDF) 8 Page - Linear Technology |
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LTC1417AIGN Datasheet(HTML) 8 Page - Linear Technology |
8 / 32 page 8 LTC1417 Load Circuits for Access Timing Load Circuits for Output Float Delay CONVST (Pin 13): Conversion Start Signal. This active low signal starts a conversion on its falling edge. BUSY (Pin 14): The BUSY output shows the converter status. It is low when a conversion is in progress. VSS (Pin 15): Negative Supply, –5V for Bipolar Operation. Bypass to AGND using 10 µF tantalum in parallel with 0.1 µF ceramic. Analog ground for unipolar operation. VDD (Pin 16): 5V Positive Supply. Bypass to AGND with 10 µF tantalum in parallel with 0.1µF ceramic. PIN FUNCTIONS TEST CIRCUITS FUNCTIONAL BLOCK DIAGRA 1k CL DOUT DGND A) HI-Z TO VOH AND VOL TO VOH CL DOUT 1k 5V B) HI-Z TO VOL AND VOH TO VOL DGND 1417 TC01 1k 30pF DOUT A) VOH TO HI-Z 30pF DOUT 1k 5V B) VOL TO HI-Z 1417 TC02 14-BIT CAPACITIVE DAC COMP REF AMP 2.5V REF 8k REFCOMP (4.096V) CSAMPLE CSAMPLE DOUT BUSY CONTROL LOGIC CONVST RD CLKOUT SHDN INTERNAL CLOCK EXTCLKIN MUX ZEROING SWITCHES SCLK VDD 16 15 9 7 14 8 12 13 11 6 10 5 4 3 2 1 AIN + AIN – VREF AGND DGND 14 1417 BD + – SUCCESSIVE APPROXIMATION REGISTER VSS (0V FOR UNIPOLAR MODE –5V FOR BIPOLAR MODE) SHIFT REGISTER |
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