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LTC1415CSW Datasheet(PDF) 6 Page - Linear Technology |
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LTC1415CSW Datasheet(HTML) 6 Page - Linear Technology |
6 / 24 page 6 LTC1415 TYPICAL PERFORMANCE CHARACTERISTICS Input Common Mode Rejection vs Input Frequency Power Supply Feedthrough vs Ripple Frequency RIPPLE FREQUENCY (Hz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 1k 100k 1M 2M LTC1415 • TPC08 10k VDD OVDD DGND INPUT FREQUENCY (Hz) 80 70 60 50 40 30 20 10 0 1k 100k 1M 2M LTC1415 • TPC09 10k PI FU CTIO S RD (Pin 22): Read Input. This enables the output drivers when CS is low. CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): The Chip Select input must be low for the ADC to recognize CONVST and RD inputs. BUSY (Pin 25): The BUSY output shows the converter status. It is low when a conversion is in progress. Its rising edge may be used to latch the output data. 0VDD (Pin 26): Digital output buffer supply. Short to Pin 28 for 5V output. Tie to 3V for driving 3V logic. DVDD (Pin 27): 5V Positive Supply. Short to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10 µF tantalum in parallel with 0.1µF or 10µF ceramic. +AIN (Pin 1): Positive Analog Input, 0V to 4.096V. –AIN (Pin 2): Negative Analog Input, 0V to 4.096V. VREF (Pin 3): 2.50V Reference Output. REFCOMP (Pin 4): Bypass to AGND with 10 µF tantalum in parallel with 0.1 µF or 10µF ceramic. AGND (Pin 5): Analog Ground. D11 to D4 (Pins 6 to 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground. D3 to D0 (Pins 15 to 18): Three-State Data Outputs. OGND (Pin 19): Digital Output Buffer Ground. NAP/SLP (Pin 20): Power Shutdown Mode. High for quick wake-up Nap mode. SHDN (Pin 21): Power Shutdown Input. A low logic level will invoke the Shutdown mode selected by the NAP/SLP pin. Tie high if unused. |
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