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LTC1415CG Datasheet(PDF) 8 Page - Linear Technology |
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LTC1415CG Datasheet(HTML) 8 Page - Linear Technology |
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8 / 24 page  8 LTC1415 APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1415 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microproces- sors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal differential 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the +AIN and –AIN inputs are con- nected to the sample-and-hold capacitors (CSAMPLE) dur- ing the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 150ns will provide enough time for the sample- and-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches the connect CSAMPLE capacitors to ground, trans- ferring the differential analog input charge onto the sum- ming junction. This input charge is successively compared with the binary weighted charges supplied by the differen- tial capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differ- ential DAC output balances the + AIN and – AIN input charges. The SAR contents (a 12-bit data word) which represents the difference of + AIN and –AIN are loaded into the 12-bit output latches. DYNAMIC PERFORMANCE The LTC1415 has excellent high speed sampling capabil- ity. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using a FFT algo- rithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1415 FFT plot. Figure 1. Simplified Block Diagram COMP +CSAMPLE –CDAC • • • D11 D0 ZEROING SWITCHES HOLD HOLD +AIN –AIN +CDAC –CSAMPLE 12 LTC1415 • F01 + – SAR OUTPUT LATCHES +VDAC –VDAC HOLD HOLD SAMPLE SAMPLE FREQUENCY (kHz) 0 0 –20 –40 –60 –80 –100 –120 100 200 300 400 LTC1415 • F02 500 600 fSAMPLE = 1.25MHz fIN = 99.792kHz SFDR - 87.5 SINAD = 72.1 Figure 2. LTC1415 Nonaveraged, 4096 Point FFT Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] or SINAD is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical spectral content with a 1.25MHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to the Nyquist limit of 625kHz. |
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