 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LTC1416CG Datasheet(PDF) 7 Page - Linear Technology |
|
||||||||||||||||||||||||||||||
LTC1416CG Datasheet(HTML) 7 Page - Linear Technology |
|
|
7 / 20 page  7 LTC1416 TEST CIRCUITS 1k CL CL DBN (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL DBN 1k 5V 1416 TC01 Load Circuits for Access Timing Load Circuits for Output Float Delay 1k 100pF 100pF DBN (A) VOH TO Hi-Z (B) VOL TO Hi-Z DBN 1k 5V 1416 TC02 APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1416 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microproces- sors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN+ and AIN– inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 400ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively com- pared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN– input charges. The SAR contents (a 14-bit data word) which represents the difference of AIN+ and AIN– are loaded into the 14-bit output latches. SAMPLE SAMPLE CSAMPLE + CSAMPLE – VDAC – VDAC + • • • D13 D0 ZEROING SWITCHES AIN + CDAC + CDAC – AIN – 14 1416 F01 COMP + – HOLD HOLD HOLD HOLD OUTPUT LATCH SAR Figure 1. Simplified Block Diagram |
Similar Part No. - LTC1416CG |
|
Similar Description - LTC1416CG |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
