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LTC1400 Datasheet(PDF) 4 Page - Linear Technology

Part No. LTC1400
Description  Complete SO-8, 12-Bit, 400ksps ADC with Shutdown
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com
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LTC1400 Datasheet(HTML) 4 Page - Linear Technology

 
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4
LTC1400
(Note 5)
DIGITAL I PUTS AND OUTPUTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IOZ
Hi-Z Output Leakage DOUT
VOUT = 0V to VCC
q
±10
µA
COZ
Hi-Z Output Capacitance DOUT (Note 7)
15
pF
ISOURCE
Output Source Current
VOUT = 0
– 10
mA
ISINK
Output Sink Current
VOUT = VCC
10
mA
TI I G CHARACTERISTICS (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
(Note 6)
q
400
kHz
tCONV
Conversion Time
fCLK = 6.4MHz
q
2.1
µs
tACQ
Acquisition Time (Unipolar Mode)
(Note 7)
q
230
300
ns
(Bipolar Mode VSS = – 5V)
q
200
270
ns
fCLK
CLK Frequency
q
0.1
6.4
MHz
tCLK
CLK Pulse Width
(Note 7)
q
50
ns
tWK(NAP)
Time to Wake Up from Nap Mode
(Note 7)
350
ns
t1
CLK Pulse Width to Return to Active Mode
q
50
ns
t2
CONV
↑ to CLK↑Setup Time
q
80
ns
t3
CONV
↑After Leading CLK↑
q
0ns
t4
CONV Pulse Width
(Note 11)
q
50
ns
t5
Time from CLK
↑to Sample Mode
(Note 7)
80
ns
t6
Aperture Delay of Sample-and-Hold
Jitter < 50ps (Note 7)
q
45
65
ns
t7
Minimum Delay Between Conversion (Unipolar Mode)
q
265
385
ns
(Bipolar Mode VSS = – 5V)
q
235
355
ns
t8
Delay Time, CLK
↑ to DOUT Valid
CLOAD = 20pF
q
40
80
ns
t9
Delay Time, CLK
↑to DOUT Hi-Z
CLOAD = 20pF
q
40
80
ns
t10
Time from Previous Data Remains Valid After CLK
CLOAD = 20pF
q
14
25
ns
The q denotes specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below VSS (ground for unipolar
mode) or above VCC, they will be clamped by internal diodes. This product
can handle input currents greater than 40mA below VSS (ground for
unipolar mode) or above VCC without latch-up.
Note 4: When these pin voltages are taken below VSS (ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 40mA below VSS (ground for unipolar mode)
without latch-up. These pins are not clamped to VCC.
Note 5: VCC = 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Recommended operating conditions.
Note 7: Guaranteed by design, not subject to test.
Note 8: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 9: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 10: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 11: The rising edge of CONV starts a conversion. If CONV returns
low at a bit decision point during the conversion, it can create small errors.
For best performance ensure that CONV returns low either within 120ns
after conversion starts (i.e., before the first bit decision) or after the 14
clock cycle. (Figure 13 Timing Diagram).


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