4

LTC1400

(Note 5)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

q

±10

µA

15

pF

Output Source Current

– 10

mA

Output Sink Current

10

mA

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Maximum Sampling Frequency

(Note 6)

q

400

kHz

Conversion Time

q

2.1

µs

Acquisition Time (Unipolar Mode)

(Note 7)

q

230

300

ns

q

200

270

ns

CLK Frequency

q

0.1

6.4

MHz

CLK Pulse Width

(Note 7)

q

50

ns

Time to Wake Up from Nap Mode

(Note 7)

350

ns

CLK Pulse Width to Return to Active Mode

q

50

ns

CONV

↑ to CLK↑Setup Time

q

80

ns

CONV

↑After Leading CLK↑

q

0ns

CONV Pulse Width

(Note 11)

q

50

ns

Time from CLK

↑to Sample Mode

(Note 7)

80

ns

Aperture Delay of Sample-and-Hold

Jitter < 50ps (Note 7)

q

45

65

ns

Minimum Delay Between Conversion (Unipolar Mode)

q

265

385

ns

q

235

355

ns

Delay Time, CLK

q

40

80

ns

Delay Time, CLK

q

40

80

ns

Time from Previous Data Remains Valid After CLK

↑

q

14

25

ns

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to GND.

mode), they will be clamped by internal diodes. This product can handle

specified.

Note 6: Recommended operating conditions.

Note 7: Guaranteed by design, not subject to test.

Note 8: Linearity, offset and full-scale specifications apply for unipolar and

bipolar modes.

Note 9: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 10: Bipolar offset is the offset voltage measured from – 0.5LSB when

the output code flickers between 0000 0000 0000 and 1111 1111 1111.

Note 11: The rising edge of CONV starts a conversion. If CONV returns

low at a bit decision point during the conversion, it can create small errors.

For best performance ensure that CONV returns low either within 120ns

after conversion starts (i.e., before the first bit decision) or after the 14

clock cycle. (Figure 13 Timing Diagram).