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VS-P101 Datasheet(PDF) 2 Page - Vishay Siliconix

Part No. VS-P101
Description  Power Modules, Passivated Assembled Circuit Elements
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Maker  VISHAY [Vishay Siliconix]
Homepage  http://www.vishay.com
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VS-P101 Datasheet(HTML) 2 Page - Vishay Siliconix

   
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VS-P100 Series
www.vishay.com
Vishay Semiconductors
Revision: 27-Mar-14
2
Document Number: 93754
For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
ON-STATE CONDUCTION
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
Maximum DC output current at case
temperature
IO
Full bridge
25
A
85
°C
Maximum peak, one-cycle non-repetitive
on-state or forward current
ITSM,
IFSM
t = 10 ms
No voltage
reapplied
Sinusoidal half wave,
initial TJ = TJ maximum
357
A
t = 8.3 ms
375
t = 10 ms
100 % VRRM
reapplied
300
t = 8.3 ms
315
Maximum I2t for fusing
I2t
t = 10 ms
No voltage
reapplied
637
A2s
t = 8.3 ms
580
t = 10 ms
100 % VRRM
reapplied
450
t = 8.3 ms
410
Maximum I2
t for fusing
I2
t
t = 0.1 ms to 10 ms, no voltage reapplied
I2t for time tx = I2
t · tx
6365
A2
s
Maximum value of threshold voltage
VT(TO)
TJ = 125 °C
0.82
V
Maximum level value of on-state slope
resistance
rt1
TJ = 125 °C, average power = VT(TO) x IT(AV) + rt + (IT(RMS))2
12
m
Maximum on-state voltage drop
VTM
ITM =  x IT(AV)
TJ = 25 °C
1.35
V
Maximum forward voltage drop
VFM
IFM =  x IF(AV)
TJ = 25 °C
1.35
V
Maximum non-repetitive rate of rise of
turned-on current
dI/dt
TJ = 125 °C from 0.67 VDRM
ITM =  x IT(AV), Ig = 500 mA, tr < 0.5 μs, tp > 6 μs
200
A/μs
Maximum holding current
IH
TJ = 25 °C anode supply = 6 V, resistive load, gate open
130
mA
Maximum latching current
IL
TJ = 25 °C anode supply = 6 V, resistive load
250
BLOCKING
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
Maximum critical rate of rise of off-state
voltage
dV/dt
TJ = 125 °C, exponential to 0.67 VDRM gate open
200
V/μs
Maximum peak reverse and off-state
leakage current at VRRM, VDRM
IRRM,
IDRM
TJ = 125 °C, gate open circuit
10
mA
Maximum peak reverse leakage current
IRRM
TJ = 25 °C
100
μA
RMS isolation voltage
VISOL
50 Hz, circuit to base, all terminals shorted,
TJ = 25 °C, t = 1 s
2500
V
TRIGGERING
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
Maximum peak gate power
PGM
8
W
Maximum average gate power
PG(AV)
2
Maximum peak gate current
IGM
2A
Maximum peak negative gate voltage
-VGM
10
V
Maximum gate voltage required to trigger
VGT
TJ = - 40 °C
Anode supply =
6 V resistive load
3
V
TJ = 25 °C
2
TJ = 125 °C
1
Maximum gate current required to trigger
IGT
TJ = - 40 °C
90
mA
TJ = 25 °C
60
TJ = 125 °C
35
Maximum gate voltage that will not trigger
VGD
TJ = 125 °C, rated VDRM applied
0.2
V
Maximum gate current that will not trigger
IGD
2mA


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