LTC1068IG-50 datasheet(6/28 Pages) LINER

Part #	LTC1068IG-50

Description	Clock-Tunable, Quad Second Order, Filter Building Blocks

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Manufacturer	LINER [Linear Technology]

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6

LTC1068 Series

ELECTRICAL CHARACTERISTICS

Table 1. Output DC Offsets One 2nd Order Section

MODE

VOSN

VOSBP

VOSLP

1VOS1[(1/Q) + 1 + ||HOLP||] – VOS3/Q

VOS3

VOSN – VOS2

1b

VOS1[(1/Q) + 1 + R2/R1] – VOS3/Q

VOS3

~(VOSN – VOS2)(1 + R5/R6)

2[VOS1(1 + R2/R1 + R2/R3 + R2/R4) – VOS3(R2/R3)X

VOS3

VOSN – VOS2

[R4/(R2 + R4)] + VOS2[R2/(R2 + R4)]

3VOS2

VOS3

VOS1[1 + R4/R1 + R4/R2 + R4/R3] – VOS2(R4/R2) – VOS3(R4/R3)

LTC1068

Maximum Q vs Center Frequency

(Modes 1, 1b, 2)

CENTER FREQUENCY, fO (kHz)

0

AB

C

0

5

15

20

25

50

35

20

40

50

1068 G01

10

40

45

30

10

30

60

70

A. VS = 3.3V, fCLK(MAX) = 1.5MHz

B. VS = 5V, fCLK(MAX) = 3.4MHz

C. VS = ±5V, fCLK(MAX) = 5.6MHz

(FOR MODE 2 R4

≥ 10R2)

LTC1068-200

Maximum Q vs Center Frequency

(Modes 1, 1b, 2)

CENTER FREQUENCY, fO (kHz)

0

A

BC

55

50

45

40

35

30

25

20

15

10

5

0

8

16

20

24

1068 G03

4

12

28

32

A: VS = 3.3V, fCLK(MAX) = 1.2MHz

B: VS = 5V, fCLK(MAX) = 3.2MHz

C: VS = ±5V, fCLK(MAX) = 6.1MHz

(FOR MODE 2, R4

≥ 10R2)

TYPICAL PERFORMANCE CHARACTERISTICS

LTC1068

Maximum Q vs Center Frequency

(Modes 2, 3)

CENTER FREQUENCY, fO (kHz)

0

AB

C

0

5

15

20

25

50

35

20

40

50

1068 G02

10

40

45

30

10

30

60

A. VS = 3.3V, fCLK(MAX) = 1MHz

B. VS = 5V, fCLK(MAX) = 3MHz

C. VS = ±5V, fCLK(MAX) = 5MHz

(FOR MODE 2 R4 < 10R2)

LTC1068-25 (Complete Filter) VS = ±5V, TA = 25°V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC Offset Voltage (Note 5)

VS = ±5V, fCLK = 1MHz, VOS1

q

0

±15

mV

(See Table 1)

(DC Offset of Input Inverter)

VS = ±5V, fCLK = 1MHz, VOS2

q

–2

±25

mV

(DC Offset of First Integrator)

VS = ±5V, fCLK = 1MHz, VOS3

q

–5

±40

mV

(DC Offset of Second Integrator)

Clock Feedthrough

VS = ±5V, fCLK = 1MHz

0.25

mVRMS

Max Clock Frequency (Note 6)

VS = ±5V, Q ≤ 1.6, Mode 1

5.6

MHz

Power Supply Current

VS = 3.14V, fCLK = 1MHz (Note 2)

q

3.5

8

mA

VS = 4.75V, fCLK = 1MHz (Note 3)

q

6.5

11

mA

VS = ±5V, fCLK = 1MHz

q

9.5

15

mA

The q denotes specifications which apply over the full operating

temperature range.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: Production testing for single 3.14V supply is achieved by

using the equivalent dual supplies of

±1.57V.

Note 3: Production testing for single 4.75V supply is achieved by

using the equivalent dual supplies of

±2.375V.

Note 4: Pin 7 (AGND) is the internal analog ground of the device. For

single supply applications this pin should be bypassed with a 1

µF

capacitor. The biasing voltage of AGND is set with an internal resistive

divider from Pin 8 to Pin 23 (see Block Diagram).

Note 5: Side D is guaranteed by design.

Note 6: See Typical Performance Characteristics.

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