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LTC1064-7M Datasheet(PDF) 9 Page - Linear Technology |
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LTC1064-7M Datasheet(HTML) 9 Page - Linear Technology |
9 / 12 page 9 LTC1064-7 PI FU CTIO S Power Supply Pins (4, 12) The V + (pin 4) and the V – (pin 12) should be bypassed with a 0.1 µF capacitor to an adequate analog ground. The filter’s power supplies should be isolated from other digital or high voltage analog supplies. A low noise linear supply is recommended. Using a switching power supply will lower the signal-to-noise ratio of the filter. The supply during power-up should have a slew rate less than 1V/ µs. When V + is applied before V– and V– is allowed to go above ground, a signal diode should clamp V – to prevent latch-up. Figures 2 and 3 show typical connections for dual and single supply operation. Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 50:1 Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 50:1 Clock Input Pin (11) Any TTL or CMOS clock source with a square-wave output and 50% duty cycle ( ±10%) is an adequate clock source for the device. The power supply for the clock source should not be the filter’s power supply. The analog ground for the filter should be connected to clock’s ground at a single point only. Table 7 shows the clock’s low and high level threshold values for a dual or single supply operation. A pulse generator can be used as a clock source provided the high level ON time is greater than 0.1 µs.Sinewavesare not recommended for clock input frequencies less than 100kHz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time ≤ 1µs). The clock signal should be routed from the right side of the IC package and perpendicular to it to avoid coupling to any input or output analog signal path. A 200 Ω resistor between clock source and pin 11 will slow down the rise and fall times of the clock to further reduce charge coupling (Figures 2 and 3). Table 7. Clock Source High and Low Threshold Levels POWER SUPPLY HIGH LEVEL LOW LEVEL Dual Supply = ±7.5V ≥ 2.18V ≤ 0.5V Dual Supply = ±5V ≥ 1.45V ≤ 0.5V Dual Supply = ±2.5V ≥ 0.73V ≤ – 2.0V Single Supply = 12V ≥ 7.80V ≤ 6.5V Single Suppl = 5V ≥ 1.45V ≤ 0.5V Analog Ground Pins (3, 5) The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the pack- age is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation, pin 3 should be connected to the analog ground plane. For single supply operation pin 3 should be biased at 1/2 supply and should be bypassed to the analog ground plane with at least a 1 µF capacitor (Figure 3). For single 5V operation at the highest fCLK of 2MHz, pin 3 should be biased at 2V. This minimizes passband gain and phase variations. Ratio Input Pin (10) The DC level at this pin determines the ratio of the clock frequency to the cutoff frequency of the filter. Pin 10 at V + gives a 50:1 ratio and pin 10 at V – gives a 100:1 ratio. For single supply operation the ratio is 50:1 when pin 10 is at V + and 100:1 when pin 10 is at ground. When pin 10 is not tied to ground, it should be bypassed to analog ground 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VIN V+ 200 Ω V– VOUT LTC1064-7 DIGITAL SUPPLY + GND CLOCK SOURCE 1064-7 F02 0.1 µF 0.1 µF V+ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VIN V+ 200 Ω VOUT DIGITAL SUPPLY + GND CLOCK SOURCE 1064-7 F03 + LTC1064-7 0.1 µF 1 µF 10k 10k V+ |
Similar Part No. - LTC1064-7M |
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Similar Description - LTC1064-7M |
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