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LTC2376-16 Datasheet(PDF) 15 Page - Linear Technology |
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LTC2376-16 Datasheet(HTML) 15 Page - Linear Technology |
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15 / 24 page  LTC2376-16 15 237616f TIMING AND CONTROL CNV Timing The LTC2376-16 conversion is controlled by CNV. A ris- ing edge on CNV will start a conversion and power up the LTC2376-16.Onceaconversionhasbeeninitiated,itcannot berestarteduntiltheconversioniscomplete.Foroptimum performance, CNV should be driven by a clean low jitter signal. Converter status is indicated by the BUSY output which remains high while the conversion is in progress. To ensure that no errors occur in the digitized results, any additional transitions on CNV should occur within 40ns from the start of the conversion or after the conversion has been completed. Once the conversion has completed, the LTC2376-16 powers down and begins acquiring the input signal. Acquisition AproprietarysamplingarchitectureallowstheLTC2376-16 to begin acquiring the input signal for the next conver- sion 527ns after the start of the current conversion. This extends the acquisition time to 3.46µs, easing settling requirements and allowing the use of extremely low power ADC drivers. (Refer to the Timing Diagram.) Internal Conversion Clock The LTC2376-16 has an internal clock that is trimmed to achieve a maximum conversion time of 3µs. Auto Power-Down The LTC2376-16 automatically powers down after a con- version has been completed and powers up once a new conversion is initiated on the rising edge of CNV. During power down, data from the last conversion can be clocked out. To minimize power dissipation during power down, disableSDOandturnoffSCK.Theautopower-downfeature will reduce the power dissipation of the LTC2376-16 as the sampling frequency is reduced. Since power is con- sumed only during a conversion, the LTC2376-16 remains powered-down for a larger fraction of the conversion cycle (tCYC) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in Figure 12. applicaTions inForMaTion DIGITAL INTERFACE The LTC2376-16 has a serial digital interface. The flexible OVDD supply allows the LTC2376-16 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The serial output data is clocked out on the SDO pin when anexternalclockisappliedtotheSCKpinifSDOisenabled. Clocking out the data after the conversion will yield the best performance. With a shift clock frequency of at least 20MHz, a 250ksps throughput is still achieved. The serial output data changes state on the rising edge of SCK and can be captured on the falling edge or next rising edge of SCK. D15 remains valid till the first rising edge of SCK. The serial interface on the LTC2376-16 is simple and straightforwardtouse.Thefollowingsectionsdescribethe operation of the LTC2376-16. Several modes are provided depending on whether a single or multiple ADCs share the SPI bus or are daisy-chained. SAMPLING RATE (kHz) 0 50 100 250 200 150 0 1.0 0.8 0.4 0.2 0.6 1.6 1.4 1.2 237616 F12 IVDD IREF IOVDD Figure 12. Power Supply Current of the LTC2376-16 Versus Sampling Rate |
Similar Part No. - LTC2376-16_15 |
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Similar Description - LTC2376-16_15 |
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