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LTC2323-16 Datasheet(PDF) 5 Page - Linear Technology

Part # LTC2323-16
Description  Dual, 16-Bit, 5Msps Differential Input ADC with Wide Input Common Mode Range
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2323-16 Datasheet(HTML) 5 Page - Linear Technology

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LTC2323-16
5
232316fa
For more information www.linear.com/LTC2323-16
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground, or above VDD
or OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground, or above VDD or OVDD, without
latch-up.
Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2 = 4.096V, fSMPL = 5MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or
+FS un-trimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±4.096V input
with REFIN = 4.096V.
Note 9: When REFOUT1,2 is overdriven, the internal reference buffer must
be turned off by setting REFINT = 0V.
Note 10: fSMPL = 5MHz, IREFBUF varies proportionally with sample rate.
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OVDD = 1.71V and
OVDD = 2.5V.
Note 13: tSCK of 9.4ns maximum allows a shift clock frequency up to
105MHz for rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: CNV is driven from a low jitter digital source, typically at OVDD
logic levels. This input pin has a TTL style input that will draw a small
amount of current.
Figure 1. Voltage Levels for Timing Specifications
0.8 • OVDD
0.2 • OVDD
50%
50%
232316 F01
0.2 • OVDD
0.8 • OVDD
0.2 • OVDD
0.8 • OVDD
tDELAY
tWIDTH
tDELAY
ADC TIMING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSMPL
Maximum Sampling Frequency
l
5
Msps
tCYC
Time Between Conversions
(Note 11)
l
200
1000000
ns
tACQ
Acquisition Time
(Note 11)
l
28.5
ns
tCONV
Conversion Time
l
171.5
ns
tCNVH
CNV High Time
l
25
ns
tDCNVSCKL
SCK Quiet Time from CNV
(Note 11)
l
9.5
ns
tDSCKLCNVH
SCK Delay Time from CNV
(Note 11)
l
19.1
ns
tSCK
SCK Period
(Notes 12, 13)
l
9.4
ns
tSCKH
SCK High Time
l
4
ns
tSCKL
SCK Low Time
l
4
ns
tDSCKCLKOUT
SCK to CLKOUT Delay
(Note 12)
l
3
ns
tDCLKOUTSDOV
SDO Data Valid Delay from CLKOUT
CL = 5pF (Note 12)
l
2
ns
tHSDO
SDO Data Remains Valid Delay from
CLKOUT
CL = 5pF (Note 11)
l
2
ns
tDCNVSDOV
SDO Data Valid Delay from CNV
CL = 5pF (Note 11)
l
2.5
3
ns
tDCNVSDOZ
Bus Relinquish Time After CNV
(Note 11)
l
3
ns
tWAKE
REFOUT1,2 Wakeup Time
CREFOUT1,2 = 10μF
10
ms
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).


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