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LT1767EMS8-1.8 Datasheet(PDF) 11 Page - Linear Technology |
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LT1767EMS8-1.8 Datasheet(HTML) 11 Page - Linear Technology |
11 / 16 page 11 LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5 sn1767 1767fas APPLICATIONS INFORMATION prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at input voltages less than twice output voltage. Higher inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory of slope compensation. LAYOUT CONSIDERATIONS As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum efficiency, switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted, the high speed switching current path, shown in Figure 5, must be kept as short as possible. This is implemented in the suggested layout of Figure 6. Shorten- ing this path will also reduce the parasitic trace inductance of approximately 25nH/inch. At switch off, this parasitic inductance produces a flyback spike across the LT1767 switch. When operating at higher currents and input voltages, with poor layout, this spike can generate volt- ages across the LT1767 that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. Board layout also has a significant effect on thermal resistance. Soldering the exposed pad to as large a copper area as possible and placing feedthroughs under the pad to a ground plane, will reduce die temperature and in- crease the power capacity of the LT1767. For the nonexposed package, Pin 4 is connected directly to the pad inside the package. Similar treatment of this pin will result in lower die temperatures. THERMAL CALCULATIONS Power dissipation in the LT1767 chip comes from four sources: switch DC loss, switch AC loss, boost circuit current, and input quiescent current. The following formulas show how to calculate each of these losses. These formulas assume continuous mode operation, so they should not be used for calculating efficiency at light load currents. Switch loss: P RI V V ns I V f SW SW OUT OUT IN OUT IN = () ( ) + ()( )( ) 2 17 Boost current loss for VBOOST = VOUT: P VI V BOOST OUT OUT IN = () 2 50 / Quiescent current loss: PV QIN = () 0 001 . RSW = Switch resistance (≈ 0.27Ω when hot) 17ns = Equivalent switch current/voltage overlap time f = Switch frequency Example: with VIN = 10V, VOUT = 5V and IOUT = 1A: P W PW PW SW BOOST Q = ( )( )() + ()()( )() =+ = = ()( ) = = ()= − 027 1 5 10 17 10 1 10 1 25 10 0 135 0 21 0 34 51 50 10 005 10 0 001 0 01 2 96 2 . •. • .. . / . .. Figure 5. High Speed Switching Path 1767 F05 5V L1 SW VIN LT1767 D1 C1 C3 VIN HIGH FREQUENCY CIRCULATING PATH LOAD The VC and FB components should be kept as far away as possible from the switch and boost nodes. The LT1767 pinout has been designed to aid in this. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation. |
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